Hi im trying to design a SAR ADC for a undegrade project, in order to choose the DAC architecture im interested into rail-to-rial input, fully diferential, my question is if the common mode is desirable to be arbitrary because ive read many papers on adc and no metion on common-mode values. I did some simulation with a monotonic DAC, and i realized that if cm voltage is below than vref/2 the DAC generates negative values ay comparator´s input leading to errors. Does anyone if its a stanrdad to use Vcm=Vdd/2 as a restriction?

Hello @Jesus Avila, it would be a good idea to send the question in the new open source silicon forum: https://fossi-chat.org There's an analog-design channel there too

HI @Jorge Marin thank you!