Hi! I'm trying to investigate why FABulous FPGA tiles seem to be struggling with routing more in newer openlane than they did in the past (since about late 2021). I've noticed is that while older OpenLANE spread macro pins out across the whole tile macro length (first screenshot), newer openlane seems to space them a lot closer (second screenshot) and I think this is hurting things a bit when pushing the limits as much as we do. Ideally we'd actually have full control over pin placement so we can play tricks like having pins aligned between 1x and 2x height macros for example (so they can perfectly abut), is there a better way to do this than just going in and patching the def after floorplan?

@gatecat you can check and adjust some constraits/variables in <OPENLANE_ROOT>/scripts/openroad/ioplacer.tcl to fit the size. We did modify some for the old versions.

Also: You can use def template with pins. @gatecat

thanks for the help here, I'm now using a custom def file with a spread-out pin layout and it's routing much better (and the tile alignment issues can be fixed this way too)

@Matt Venn we have discussed here