Anyone knows what is the maximum bandwidth of the bare wire analog pads ?

Not sure how to interpret the question correctly, but the chip pad usually has a connection from the PCB through the package to the chip pad. Depending on package type this is mostly inductive (especially when bondwire). Then on-chip there is the pad capacitance to substrate plus the ESD protection plus whatever is connected circuit. Rule of thumbs: Trace/bondwire is ca. 1nH/mm Chip pad is ca. 0.15pF ESD is somewhere 0.2-0.4pF Add these to the circuit and simulate their impact.

There is a bare wire analog connection to the chip. What is the maximum bandwidth signal that could go through it

@Harald Pretl: The straight-through wires have no ESD, so it is possible to maximize the bandwidth by ignoring ESD completely (and having a very ESD-sensitive device). Also, the WLCSP version (on Open MPW runs) doesn't have bondwires, but I'm not sure what the appropriate model would be. @Talha Bin Azmat: I expect that you should be able to get "something above" 1GHz. Based on other chips I have designed in similar processes, the frequency tended to roll off around 2-3 GHz. But I would not try to assert any value with any accuracy without at least trying to model it with some back-of-the-envelope calculations. There might be some analog projects from MPW-two that can be used to directly test the performance limits of the analog pads on caravan.