@Tim Edwards Hi Tim, I have a crossbar array with certain structure. And my inputs to the array through the analog pads are reverse ramp signal (3V or less level and frequency <1MHz). 1. Can the analog pad takes a reverse ramp signal. 2. Is it possible to program the SoC to generate a such signal to the analog pads or I have to give it from outside (function generator)? 3. I have a 4-16 decoder built from HV standard library, can I send the four bits from the SoC (0 for bit 0, and 3.3V for bit 1)? Thanks!

1. And my inputs to the array through the analog pads are reverse ramp signal (3V or less level and frequency <1MHz)" Is it negative? The bare pads can endure that, but you need ESD protection that works with negative voltages (the non bare pads have a diode from ground to pad, making negative voltages on pads impossible) 2. "Is it possible to program the SoC to generate a such signal to the analog pads or I have to give it from outside (function generator)?" There is no ready to use DAC in caravan mgmt area. Therefore you need to design it in order to use. 3. Yes you can, but you will need to level shift the outputs, since mgmt area uses 1.8V

@Arman Avetisyan Thanks for your response! For 1: No, my signal is positive. However, can the pad accept a ramp signal if I connect it to gpio_analog pr gpio_noesd? For 3: doesn't the caravan has io_in_3v3 signal for hv standard cell. Do I still need a level shifter?

1. I am not familiar with "ramp" signals, but if it is analog then it can be used. Keep in mind that gpio_analog and gpio_noesd have different connections. gpio_analog is connected with 150 ohm resistor, the gpio_noesd may need extra esd protection. 3. The io_in_3v3 is digital 3v3 gpio signal, but I was referring to the mgmt area signals, they are 1v8

@Arman Avetisyan 3: so the 3v3 gpio is in case I tke the digital inputs from outside,right ? But if I am taking the digital signals from the mgmt SoC, I need a level shifter, right?

yes

@Abdulaziz: I would suggest using the digital I/O for analog signals <= 3.3V and < 50MHz. The pads can be put into analog mode (and can be made to come up by default in analog mode on power-up). On the caravan chip, you can also input 3.3V signals from off-chip. However, as Arman mentioned, the SoC is all running at 1.8V so you will need level shifters to bounce signal levels down to 1.8V to communicate with the SoC. The HVL library has level shifters for both directions.

Thanks @Tim Edwards My analog inputs is a ramp signal with 3 V amplitude. By saying the pad can be put into analog mode, you mean gpio_analog or gpio_noesd, right? So, in this case and since I am taking my analog signal from off chip, do I need an analog level shifter? For the SoC: I need to take the digital inputs for my decoder from it. My digital inputs of the decoder are 3.3 as bit 1 and 0 as bit 0. So in order to communicate with the SoC I need to connect my decoder inputs to digital gpio (say io_in pin) and in between I put a level shifter up to 3.3 V, right?

@Abdulaziz: Yes, you would connect to

gpio_analog

(only use

gpio_noesd

if you cannot tolerate a 150 ohm resistor in series with the input). But "put into analog mode" means to set the default GPIO configuration for that pin (and/or set the GPIO configuration from software) to turn off the digital input and output buffers. That's required to use the GPIO pin as an analog signal. For the digital inputs, there is (on the

caravan

version of the chip) a

io_in_3v3

signal as well as the `io_in`; the first one is a copy of the 2nd, in the high voltage domain. You can make use of either signal, or both. You can configure the GPIO as a user-controlled input when getting your signal from off-chip. You can then alternatively configure the GPIO (through software) as a management-controlled digital output, but with the input buffer turned on. The management SoC will then control the pad value, but the user project will still be able to read the pad input, so that you can emulate the external signal from software.

@Tim Edwards Thanks Tim! I am a little confused here regarding the digital inputs. Maybe my bad I wasn’t so clear, So I will try to make it clearer. So I have four inputs for my decoder, and would like to feed these inputs on chip from the management SoC. The way I am doing it is to couple a level shifter (lv2hv) between the decoder input and io_in pad for each of the four inputs. (since they are hv and the soc operate at 1.8V). But I don’t really understand when you say configure the gpio as management-controlled digital output. Shouldn’t be configure the gpio as management-controlled digital input? Also, how to configure the gpio as user-controlled input, via software too? My apologies for any inconvenience!

I may be confused about direction and connectivity. Can you provide a simple drawing?

@Tim Edwards sure. Here is a hand sketch. I hope it's clear

mgmt soc pins and gpio pins are not the same thing

@Arman Avetisyan Yes you're right. I was just referring to the communication between user’s pins and SoC. I believe we have access to the user's project gpio via the mgnt SoC,right?

Okay, first read the verilog code of user project wrapper. It contains answers to most of your questions. Second, the mgmt soc has two interfaces: Logic Analyzer and wishbone. Both can be used to control anything inside area Mgmt soc can also control digital gpios, either to connect control signals user area OR just control the gpios from mgmt soc. It technically can be configured to output anything and technically the input signal (connected to user area) will match the output, but why would you waste gpios, if you can control it using another interface?

Thanks!

The way I am doing it is to couple a level shifter (lv2hv) between the decoder input and io_in pad for each of the four inputs. (since they are hv and the soc operate at 1.8V).

You dont need level shifter, you can just connect to io_in_3v3

But I don’t really understand when you say configure the gpio as management-controlled digital output. Shouldn’t be configure the gpio as management-controlled digital input?

Because in order to drive the pad from mgmt you need to enable the output drivers. The input is going to match the output signal.

Also, how to configure the gpio as user-controlled input, via software too?

Via software for RISC-V CPU of the mgmt area. The software is located on external SPI Flash, if I remember correctly. In next MPW the support for design time configuration might be added, but I dont have any details regarding that.

@Arman Avetisyan “You dont need level shifter, you can just connect to io_in_3v3” But in this case (connecting to io_in_3v3 and without a level shifter) I will only have one option to feed my inputs which is from off chip, Whereas coupling a level shifter (lv2hv) and connect it to io_in, will give me two options to feed the input, either from on chip (through the mngt SoC and this is why I need a level shifter because mgnt SoC operates at 1.8V) or off chip. Am I right? In other words: if I want to feed my inputs from off chip, i connect them to io_in_3v3 If I want to feed my inputs from on chip, I connect them to io_in and a lv2hv level shifter in between