Hello everyone. I am exploring OpenRAM and want to create a RAM memory (requirement: 16x128, single rw port) . I am getting LVS error. I have also attached my config.py file. I noticed that incase I switch from 1rw port to 2rw port, then i dont get any error. Why is that so ???

ERROR: file simulation.py: line 605: Could not find bl net in timing paths.
Traceback (most recent call last):
  File "sram_compiler.py", line 76, in <module>
    s.save()
  File "/mnt/c/Users/Iyer/OpenRAM/compiler/sram.py", line 130, in save
    d.analysis_init(probe_address, probe_data)
  File "/mnt/c/Users/Iyer/OpenRAM/compiler/characterizer/delay.py", line 1288, in analysis_init
    self.set_internal_spice_names()
  File "/mnt/c/Users/Iyer/OpenRAM/compiler/characterizer/simulation.py", line 520, in set_internal_spice_names
    bl_name_port, br_name_port = self.get_bl_name(self.graph.all_paths, port)
  File "/mnt/c/Users/Iyer/OpenRAM/compiler/characterizer/simulation.py", line 624, in get_bl_name
    bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set))
  File "/mnt/c/Users/Iyer/OpenRAM/compiler/characterizer/simulation.py", line 605, in get_alias_in_path
    debug.error("Could not find {} net in timing paths.".format(internal_net), 1)
  File "/mnt/c/Users/Iyer/OpenRAM/compiler/debug.py", line 48, in error
    assert return_value == 0
AssertionError

Hi Lakshmi, This is a well known error but we haven't had anyone to fix it yet. https://github.com/VLSIDA/OpenRAM/issues/251

Yes. I have seen this. Okay. Is it necessary to do check_lvsdrc and inline_lvsdrc (anyone or both) ??? I have seen examples where these are not present.