Hello i am in process of hardening my user proj example modu open-source-silicon.dev #lvs

Hello, i am in process of hardening my user_proj_e...

Sanchit Gupta

02/28/2025, 12:35 PM

Hello, i am in process of hardening my user_proj_example module and encountered LVS errors during signoff stage. My design includes one SRAM macro and i am using wishbone ports for reading and writing to it. I appreciate any assistance you can provide. Thank yoy!

33-user_proj_example.lef.lvs.log 33-lvs.lef.log config.json 33-user_proj_example.lef.lvs.json 33-user_proj_example.lvs.rpt user_proj_example.v

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Mitch Bailey

02/28/2025, 1:27 PM

@Sanchit Gupta I don’t see anything out of place with the

config.json

file, but you are correct in that the sram appears to be not connected power. Could you share the

macro_placement.cfg

file also?

Sanchit Gupta

02/28/2025, 2:17 PM

macro_placement.cfg -> sram0 125 625 N

Mitch Bailey

02/28/2025, 2:39 PM

Do you have a gds file that you can check? Maybe that would give some clue as to why the sram power rails aren’t connected.

Sanchit Gupta

02/28/2025, 2:56 PM

yes, i have one gds file in results directory

user_proj_example.gds

Mitch Bailey

02/28/2025, 3:19 PM

Thanks. I think I see what’s happening. The sram macro has vertical met4 pins that it expects to connect to horizontal metal5 power rails. However,

user_proj_example

does not have metal5 horizontal power rails. I think there might be a couple ways to solve this problem. 1. Do not create

user_proj_example

as a hard macro. Instead flatten it as a soft macro. You’ll need to modify the config file to do synthesis though. 2. Use the

user_proj_example

hard macro, but add met4 pins to the lef where the sram power connections should be. The

user_proj_example

will not pass LVS in the openlane flow, but should pass at the

user_project_wrapper

level. There might be another way by modifying the pdn script.

Sanchit Gupta

03/01/2025, 5:16 AM

Thank you for your suggestions! For flattening the

user_proj_example

as a soft macro, I followed your advice and removed the following commands from the config file: "FP_PDN_MACRO_HOOKS": "sram0 vccd1 vssd1 vccd1 vssd1", "MACRO_PLACEMENT_CFG": "dir::macro_placement.cfg" and added these commands also "SYNTH_TOP": "user_proj_example", "SYNTH_FLATTEN": true, After that, I re-ran the flow, but I still encountered an LVS error during the signoff stage. I suspect I might have missed something or done something wrong in the process. Could you please elaborate on the correct steps for flattening the user_proj_example as a soft macro?

Sanchit Gupta

03/01/2025, 5:17 AM

user_proj_example.gds

Sanchit Gupta

03/08/2025, 7:07 PM

@Mitch Bailey Is it always necessary to use the Caravel

user_project_wrapper

? I was thinking of making

user_proj_example

a core and hardening the SRAM macros inside it. I'm asking this because when I set

"DESIGN_IS_CORE": true

in the

config.json

file of

user_proj_example

, the OpenLane flow completes successfully without any LVS errors. Apologies if this is a silly question!

issue_reproducible.zip

Sanchit Gupta

03/08/2025, 8:02 PM

@Mitch Bailey i tried to integrate sram macros in the user_project_wrapper itself with some basic logic and i have also modified the config.json file but when i ran the flow then i am getting errors during synthesis stage

config.json user_project_wrapper.v macro.cfg

Mitch Bailey

03/09/2025, 7:11 AM

@Sanchit Gupta Sorry, I missed the reply on March 1st. First, the default

user_project_wrapper

configuration file is setup to not do synthesis. It needs to be modified to something like the

user_proj_example

config file. Second, the

user_proj_example

verilog code has not been included, so it won’t be synthesized. Third, the sram macros are now at lower level of hierarchy, so the macro.cfg file instance names need to be changed to

mprj.sram0

etc. Here’s a sample config file that might work (don’t forget to change the

macro.cfg

file). This file does not contain the

DESIGN_IS_CORE

element. It might be necessary to add that.

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{       
    "DESIGN_NAME": "user_project_wrapper",
    "VERILOG_FILES": [
        "dir::../../verilog/rtl/defines.v",
        "dir::../../verilog/rtl/user_proj_example.v",
        "dir::../../verilog/rtl/user_project_wrapper.v"
    ],
    "ROUTING_CORES": 1,
    "CLOCK_PERIOD": 25,
    "CLOCK_PORT": "wb_clk_i",
    "CLOCK_NET": "wb_clk_i",
    "FP_PDN_MACRO_HOOKS": "mprj.sram0 vccd1 vssd1 vccd1 vssd1, mprj.sram1 vccd1 vssd1 vccd1 vssd1, mprj.sram2 vccd1 vssd1 vccd1 vssd1, mprj.sram3 vccd1 vssd1 vccd1 vssd1",
    "MACRO_PLACEMENT_CFG": "dir::macro.cfg",
    "MAGIC_DEF_LABELS": 0,
    "VERILOG_FILES_BLACKBOX": [
        "dir::../../verilog/rtl/defines.v",
        "pdk_dir::libs.ref/sky130_sram_macros/verilog/sky130_sram_1kbyte_1rw1r_32x256_8.v"
    ],
    
    "EXTRA_LEFS": "pdk_dir::libs.ref/sky130_sram_macros/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef",
    "EXTRA_GDS_FILES": "pdk_dir::libs.ref/sky130_sram_macros/gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds",
    "EXTRA_LIBS": "pdk_dir::libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib", 

    "BASE_SDC_FILE": "dir::base_user_project_wrapper.sdc",
    "FP_PDN_VPITCH": 180,
    "FP_PDN_HPITCH": 180,
    "CLOCK_TREE_SYNTH": 0,
    "FP_PDN_VOFFSET": 5,
    "FP_PDN_HOFFSET": 5,
    "MAGIC_ZEROIZE_ORIGIN": 0,
    "FP_SIZING": "absolute",
    "PL_BASIC_PLACEMENT": 0,
    "PL_TARGET_DENSITY": 0.42,
    "DIODE_INSERTION_STRATEGY": 3,
    "RUN_CVC": 1,
    "RUN_KLAYOUT_XOR": false,
    "MAGIC_DRC_USE_GDS": false,
    "QUIT_ON_MAGIC_DRC": false,
    "RUN_CVC": 0,
    "UNIT": 2.4,
    "FP_IO_VEXTEND": "expr::2 * $UNIT",
    "FP_IO_HEXTEND": "expr::2 * $UNIT",
    "FP_IO_VLENGTH": "expr::$UNIT",
    "FP_IO_HLENGTH": "expr::$UNIT",
    "FP_IO_VTHICKNESS_MULT": 4,
    "FP_IO_HTHICKNESS_MULT": 4,
    "FP_PDN_CORE_RING": 1,
    "FP_PDN_CORE_RING_VWIDTH": 3.1,
    "FP_PDN_CORE_RING_HWIDTH": 3.1,
    "FP_PDN_CORE_RING_VOFFSET": 12.45,
    "FP_PDN_CORE_RING_HOFFSET": 12.45,
    "FP_PDN_CORE_RING_VSPACING": 1.7,
    "FP_PDN_CORE_RING_HSPACING": 1.7,
    "FP_PDN_VWIDTH": 3.1,
    "FP_PDN_HWIDTH": 3.1,
    "FP_PDN_VSPACING": "expr::(5 * $FP_PDN_CORE_RING_VWIDTH)",
    "FP_PDN_HSPACING": "expr::(5 * $FP_PDN_CORE_RING_HWIDTH)",
    "VDD_NETS": [
        "vccd1",
        "vccd2",
        "vdda1",
        "vdda2"
    ],
    "GND_NETS": [
        "vssd1",
        "vssd2",
        "vssa1",
        "vssa2"
    ],
    "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
    "pdk::sky130*": {
        "RT_MAX_LAYER": "met4",
        "DIE_AREA": "0 0 1500 1500",
        "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def",
        "scl::sky130_fd_sc_hd": {
            "CLOCK_PERIOD": 25
        },
        "scl::sky130_fd_sc_hdll": {
            "CLOCK_PERIOD": 10
        },
        "scl::sky130_fd_sc_hs": {
            "CLOCK_PERIOD": 8
        },
        "scl::sky130_fd_sc_ls": {
            "CLOCK_PERIOD": 10,
            "SYNTH_MAX_FANOUT": 5
        },
    },
    "pdk::gf180mcuC": {
        "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
        "FP_PDN_CHECK_NODES": 0,
        "FP_PDN_ENABLE_RAILS": 0,
        "RT_MAX_LAYER": "Metal4",
        "DIE_AREA": "0 0 3000 3000",
        "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper_gf180mcu.def",
        "PL_OPENPHYSYN_OPTIMIZATIONS": 0,
        "DIODE_INSERTION_STRATEGY": 0,
        "MAGIC_WRITE_FULL_LEF": 0
    }
}

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Sanchit Gupta

03/09/2025, 1:05 PM

Thanks @Mitch Bailey I have tried with this config.json file and now i am getting errors on DRC step.

Sanchit Gupta

03/09/2025, 6:51 PM

I have tried by adding these commands also but nothing worked. "MAGIC_DRC_USE_GDS": true, "EXCLUDE_DRC_CELLS": ["sky130_sram_1kbyte_1rw1r_32x256_8"], Also, @Mitch Bailey i found one older message by @Tim Edwards "Magic does not implement the SRAM-specific DRC rules (which are many). The solution is to keep the SRAM as an abstract view by loading from the sky130_sram_macros/maglef/ directory. There are commands in magic to swap out the full view for the abstract view using "cellname filepath" and "flush", but the easiest way is just to find the SRAM entry in the .mag file of the top level cell and change "mag" to "maglef" in the path name." But i did not get that where to change thsi mag to maglef ? Could you provide some suggestions for this.

33-drc.log 33-drc.errors

Mitch Bailey

03/10/2025, 12:05 PM

Copy code

Child killed:

usually means out of memory.

Sanchit Gupta

03/10/2025, 12:17 PM

Okay, i'll incease swap memory.

Mitch Bailey

03/11/2025, 10:51 PM

not sure. Can you post your config.json, macro.cfg, verilog rtl files?

Sanchit Gupta

03/19/2025, 5:11 AM

Sorry for delay. I am sharing all the files.

user_project_wrapper.v user_proj_example.v config.json macro.cfg

Mitch Bailey

03/19/2025, 1:16 PM

@Sanchit Gupta Those files all look good to me. Are you still stuck on drc errors in the openlane flow?

Sanchit Gupta

03/19/2025, 2:19 PM

Yes

Mitch Bailey

03/19/2025, 6:52 PM

@Sanchit Gupta There is one drc flow for srams that replaces the macro with the lef version just for drc. That might be the precheck drc. Can you try to disable the magic drc check in openlane and do the final drc check later with precheck? Try this to run drc on the LEF/DEF files

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"MAGIC_DRC_USE_GDS": 0,

or this to disable magic drc completely.

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"RUN_MAGIC_DRC": 0,

👍 1

Mitch Bailey

03/20/2025, 5:35 AM

I just noticed that you already have

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"MAGIC_DRC_USE_GDS": false,

Sanchit Gupta

03/24/2025, 4:36 PM

Thank you so much for your help, @Mitch Bailey. When I ran the DRC flow with 64GB of RAM and 128GB of OS swap memory, it completed successfully.

👍 1

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