Hey. Looks like OpenLane does not support multi hierarchy timing checks. But the example design contains connections between example block and the I/O. How did you verify the timings?

@Arman Avetisyan: I worked out a script that allows Magic to create a flattened DEF file from the chip top level, to remove hierarchy down to the level of standard cells, I/O cells, and macros like the SRAM. We are currently testing this method for doing full-chip timing checks. Once we have confirmed the method, we will send out a post to the community with instructions on how to run full-chip timing analysis for your project.