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Has anyone here looked at the SRAM22 ram compiler ...
# sky130
t
Has anyone here looked at the SRAM22 ram compiler ? Or better is anyone here in the team working on it ? I have some questions 😁 Starting with : How was the word line driver dimensionned ? It seems gigantic 😁 Like it's the same width as the whole bitcell array ...
e
tagging in @Rahul Kumar/@Rahul Kumar
r
Hey, I'm one of the developers of SRAM22. The wordline driver is sized by using the logical effort method. We calculate the ratio of the wordline capacitance to the size of a unit inverter, and use that to calculate the number of stages (based on a target per-stage fanout) and then the size of each stage. You can find the code for this here: https://github.com/rahulk29/sram22/blob/master/src/blocks/decoder/mod.rs The wordline driver could be made smaller by increasing the target per-stage fanout, though this would require a corresponding change to the control logic to increase the wordline driver pulse time. By the way, please keep in mind that the latest SRAM22 macros have not yet been tested in silicon.
m
How is this different from OpenRAM?
t
@Rahul Kumar Yes, I know it wasn't taped out yet. We were think of integrating some test macros on the upcoming TinyTapeout 10 run ( on chipignite 2504 ).
r
@Matt Liberty I was wondering the same, but just found https://github.com/rahulk29/sram22_sky130_macros/ from comparing the 256x32 memory from there with the openram generated version delivered with the sky130 pdk (not sure if the options for both match completely though) it looks like the sram22 version is more compact (422x291 um vs 479x397 um) and sram22 doesn't put any obstructions on metal 3 and 4 while openram does. Also, looking at the .lib file the reported leakage (TT, 25C) for sram22 (0.37 uW) is much better than openram's version (9.5 uW, also TT 25C)
Ah, upon closer inspection, the openram version I was looking at has 1rw+1r port and the sram22 version has only 1rw port. That explains some of the difference already
t
Yeah, I was hoping that it would come closer to the commercial SRAM macro but it's still ways out ... about 3x larger for a 1024x32 single port SRAM.
It seems way better designed than OpenRAM but still a lot of unused space in the periphery affecting density a lot :

https://i.imgur.com/SrqUq5v.png▾

The bitcell array is like 12.5% of the total macro area in the example above 😕
@Rahul Kumar I'm curious why the decision to only go up to 
metal2
? I definitely appreciate not using all the metals to make integration easier but with sky130 I would have thought going up to 
metal3
wouldn't be an issue, leaving 
met4
/ 
met5
for integration/PDN.
BTW, some pictures of a cypress chip taken by Andrew Zoneberg showing the bitcell ( https://siliconpr0n.org/archive/doku.php?id=azonenberg:cypress:cy8c4245axi )

https://i.imgur.com/qQmFdk5.png▾

And SRAM22 macro for comparison :

https://i.imgur.com/ySVTK9G.png▾

r
The main reason was that we didn't really need to do much routing on m3 inside the SRAM. Going up to only m2 leaves two 0.3um min width signal routing layers (m3/m4) above the SRAM, which can be convenient because you can place 90 degree turns over the SRAM while obeying preferred routing directions.
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