Hello, I am running a precheck that contains the PriorityEncoder mentioned above, as well as a couple other modules, but I am running into an issue. I am failing the precheck LVS check, although the wrapper passed a sole LVS check. I ran the lvs using the lvs.script file included here to include the standard cell library since the priority encoder uses standard cells. My question is: Do I have to do anything extra when running a precheck on a project that contains standard cells?

@Travis Jakl All the settings for LVS should be in

lvs/user_analog_project_wrapper/lvs_config.json

. This may be out-dated. Could you share your file? You’re talking about the local precheck, right?

make run-precheck

and not the precheck run from the Efabless website, right? precheck is currently configured to use the

1.0.470

version of the pdk for LVS while the pdk version that is currently installed on your system appears to be

1.0.424

. The

1.0.470

pdk is shasum

6d4d11780c40b20ee63cc98e645307a9bf2b2ab8

. So if you

export OPEN_PDKS_COMMIT=6d4d11780c40b20ee63cc98e645307a9bf2b2ab8
make pdk-with-volare

It should update the pdk. There may be an issue if you subsequently use openlane for digitial synthesis. Let me know if you have other problems.

@Mitch Bailey Upon updating the PDK, i still get a similar result. The priority encoder was digitally synthesized, what issues arise from this fact?

@Travis Jakl From the lvs report

Circuit 1: user_analog_project_wrapper                                            |Circuit 2: user_analog_project_wrapper
----------------------------------------------------------------------------------|----------------------------------------------------------------------------------
sky130_fd_sc_hd__decap_8 (3->1)                                                   |sky130_fd_sc_hd__decap_8 (487->1) 
sky130_fd_pr__nfet_01v8 (74->70)                                                  |sky130_fd_pr__nfet_01v8 (2458->1594) **Mismatch**
sky130_fd_pr__pfet_01v8_hvt (74->70)                                              |sky130_fd_pr__pfet_01v8_hvt (2598->1726) **Mismatch**
sky130_fd_sc_hd__decap_3 (12->1)                                                  |sky130_fd_sc_hd__decap_3 (1707->1)
sky130_fd_sc_hd__o21a_1 (1)                                                       |sky130_fd_sc_hd__o21a_1 (7) **Mismatch**
sky130_fd_sc_hd__buf_12 (4)                                                       |sky130_fd_sc_hd__buf_12 (85) **Mismatch**
sky130_fd_sc_hd__a31o_1 (1)                                                       |sky130_fd_sc_hd__a31o_1 (12) **Mismatch**
sky130_ef_sc_hd__decap_12 (4->1)                                                  |sky130_ef_sc_hd__decap_12 (275569->1)
sky130_fd_sc_hd__decap_6 (1)                                                      |sky130_fd_sc_hd__decap_6 (68063->1)
sky130_fd_sc_hd__clkbuf_1 (2)                                                     |sky130_fd_sc_hd__clkbuf_1 (2)
sky130_fd_sc_hd__buf_1 (13)                                                       |sky130_fd_sc_hd__buf_1 (43) **Mismatch**
sky130_fd_sc_hd__inv_2 (1)                                                        |sky130_fd_sc_hd__inv_2 (20) **Mismatch**
TransmissionGate (6)                                                              |(no matching element)
Inverter (7)                                                                      |(no matching element)
sky130_fd_pr__nfet_g5v0d10v5 (2)                                                  |(no matching element)
(no matching element)                                                             |sky130_fd_pr__diode_pw2nd_05v5 (765->149)
(no matching element)                                                             |sky130_fd_pr__special_nfet_01v8 (132)
(no matching element)                                                             |sky130_fd_pr__res_generic_po (262->132)
Number of devices: 181 **Mismatch**                                               |Number of devices: 3906 **Mismatch**
Number of nets: 127 **Mismatch**                                                  |Number of nets: 2104 **Mismatch**

These look like totally different designs. Does the

lvs/user_analog_project_wrapper/lvs_config.json

file list both spice and verilog for the top level? It should probably only be one of these. The previous log file had

SOURCE FILE(S): /home/tjdjakl/asic-reram-test-chip/xschem/user_analog_project_wrapper.spice
 /home/tjdjakl/asic-reram-test-chip/dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice
 /home/tjdjakl/asic-reram-test-chip/dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice
 /home/tjdjakl/asic-reram-test-chip/dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice
 /home/tjdjakl/asic-reram-test-chip/verilog/gl/user_proj_example.v
 /home/tjdjakl/asic-reram-test-chip/verilog/gl/user_analog_project_wrapper.v

Does the layout have a

user_proj_example

block?

The layout does not have a

user_proj_example

block. I do not understand why the local precheck LVS would be so drastically different than a normal LVS check. With the layout and schematic utilizing a digitally synthesized module (Priority_Encoder_16t4), is there something special I need to do with the verilog file for precheck to use it correctly?

@Travis Jakl local precheck is a full LVS check while a “normal” LVS check (if you are referring to the LVS check in openlane) abstracts all the lower level cells. local precheck requires source netlists for all the cells while openlane only requires the top level. In the

lvs_config.json

file, there is a top level spice and a top level verilog, but you only want one of those.

"LVS_SPICE_FILES_TO_FIX": [
		"$UPRJ_ROOT/xschem/user_analog_project_wrapper.spice"    <--- here 
	],
	"LVS_SPICE_FILES": [
		"$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice",
		"$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice"
	],
	"LVS_VERILOG_FILES": [
		"$UPRJ_ROOT/verilog/gl/user_proj_example.v",
		"$UPRJ_ROOT/verilog/gl/Priority_Encoder_16t4.v",
		"$UPRJ_ROOT/verilog/gl/$TOP_SOURCE.v"                    <--- here
	],

The

LVS_SPICE_FILES_TO_FIX

is no longer needed. Please include the top spice file in

LVS_SPICE_FILES

instead. This is my suggestion (assuming that you’re not using

user_proj_example.v

or

user_analog_project_wrapper.v

).

"LVS_SPICE_FILES": [
		"$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice",
		"$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice",
		"$UPRJ_ROOT/xschem/user_analog_project_wrapper.spice"
	],
	"LVS_VERILOG_FILES": [
		"$UPRJ_ROOT/verilog/gl/Priority_Encoder_16t4.v"
	],

Now I am receiving errors for OEB and LAYOUT, but it looks like the

lvs_config.json

file is the issue there. It's providing an error for

Loading LVS environment from /home/tjdjakl/asic-reram-test-chip/lvs/user_analog_project_wrapper/lvs_config.json
<class 'json.decoder.JSONDecodeError'>
('Expecting value: line 32 column 9 (char 710)',)
Error with file /home/tjdjakl/asic-reram-test-chip/lvs/user_analog_project_wrapper/lvs_config.json

The Line 32 Col 9 is the bracket right above

LAYOUT_FILE

.

The json syntax is very strict. There’s an extra comma after the verilog file name. That will give you a syntax error. Also, you don’t have to put the top level spice file in the netgen directory. Some people create it in the xschem directory. Did you create the top level in xschem?