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I'm doing some circuit simulation of a level shift...
# analog-design
m
I'm doing some circuit simulation of a level shifter and I want to find out when it stops working. I have managed a control loop that runs a transient simulation 100 times with slowly decreasing supply and input signal voltage. Then I can look at each dataset in xschem graph viewer to see where the limits are
what other techniques do people use for these types of experiments?
l
Show us your circuit, matt. The transient sim and parameter sweep is the best approach, anyway. Remember that monte carlo will affect it also.
Something we can also do is a DC sweep sim and see the circuit hysteresis. I don't think ngspice does it directly. You should run a DC sim with the input changing from ground to rail and another sim sweeping from rail to ground
m
I was thinking of a DC sweep over supply but I wanted to see the transition of the input pulse
l
Ok. This level shifter can be a bit bad if the low voltage supply is really low and the high supply is really high. For example, it may fail for 5 V vddh and 1.5 vddl. Its performance also depends on sizing, but it is really hard to break a level shifter.
This second topology is my favorite one. It's more robust for very large differences between low and high supplies. Anyway, if your circuit passes the specs, such as SF and FS corners, lowest low supply and highest high supply, you don't need to change it.
👍 1
m
check the other schematic in there
from @tnt
the bigger picture here btw is to control a small digital design's PSU inside a TT tile
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we will power it with the 3.3v analog rail so it can be controlled externally
we can't change the 1.8v because that powers the mux
then a buffer from inputs to the dut
and the level shifter between dut and outputs
t
@Luis Henrique Rodovalho Something @Matt Venn Didn't mention is that VDDL is really low for sky130 ... like potentially sub-1V and at that point you're barely above the threshold voltage of the transistors ...
l
If vddl is that low, you may get in trouble with the basic level shifter topology...
t
Yes. The one I proposed looks more like an analog comparator comparing the input with vddl/2 ...
l
An analog comparator is a bit extreme. It's performance and area can be larger than needed. I don't know if this technology has native (zero vt) high voltage, but it could be used for very low voltage inputs.
You can have very low thresholds if you use parallel transistor arrays for the NMOS and series arrays for the PMOS.
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