I've created a design and preformed rtl simulation (which passed successfully) but when preforming gl simulation the clock and most of the signals in user space are unidentified (I think they are all pulled down for some reason)

I know little about this but first check that the standard cell library files are correctly included in the simulation.

I've checked and yes they are: ########################################################### # STD CELLS - they need to be below the defines.v files ########################################################### -v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v -v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v -v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog/primitives.v -v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v -v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v -v $(PDK_ROOT)/$(PDK)/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v could it be caused due to hardening config, sdc or from the rtl itself?

@Abdullah AL Towaijri Are you simulating the

user_project_wrapper

block or the top level

caravel

?

@Mitch Bailey I’m running the make cocotb-verify-…-gl so I am almost sure it runs the full caravel with the wrapper implemented inside

@Abdullah AL Towaijri If you have already modified the

verilog/rtl/user_defines.v

to specify the default gpio configurations, then you may need to run

make gpio_defaults

to create the gate level verilog files for each configuration. Do you have the

verilog/gl/gpio_defaults_block_xxxx.v

files? In your cocotb logs, are there any messages about undefined verilog modules?

@Mitch Bailey Yes I do, No they are no warnings regarding undefined Verilog modules.

@Marwan Abbas Are you the cocotb expert or is there someone else we should ask?

@Mostafa Rady is the expert on cocotb

@Mitch Bailey Yes thanks to marwan. As for your problem make sure your verilog/includes/includes.gl…… contains the all gpio_defaults_block_xxxx files (you should find all the required gpio_defaults_…. inside verilog/gl)