< Mitch Bailey> Thank you for your suggestion it is working open-source-silicon.dev #caravel

<@U017X0NM2E7> Thank you for your suggestion, it i...

Sanchit Gupta

02/16/2025, 2:26 PM

@Mitch Bailey Thank you for your suggestion, it is working properly. But when i added 4 macros then same error is coming. I have attached the updated files for reference.

macro_placement.cfg config.json

Mitch Bailey

02/16/2025, 3:11 PM

@Sanchit Gupta Try changing

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"FP_PDN_MACRO_HOOKS": "user_proj_example.sram0 vccd1 vssd1 vccd1 vssd1, user_proj_example.sram1 vccd1 vssd1 vccd1 vssd1, user_proj_example.sram2 vccd1 vssd1 vccd1 vssd1, user_proj_example.sram3 vccd1 vssd1 vccd1 vssd1",

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"FP_PDN_MACRO_HOOKS": "sram0 vccd1 vssd1 vccd1 vssd1, sram1 vccd1 vssd1 vccd1 vssd1, sram2 vccd1 vssd1 vccd1 vssd1, sram3 vccd1 vssd1 vccd1 vssd1",

Sanchit Gupta

02/16/2025, 4:31 PM

still showing same error

Mitch Bailey

02/16/2025, 8:15 PM

@Sanchit Gupta Can you share

dir::../../verilog/rtl/user_proj_example.v

? If this is not open source, you can send it in a DM.

Sanchit Gupta

02/17/2025, 3:50 AM

user_proj_example.v

Mitch Bailey

02/17/2025, 4:38 AM

@Sanchit Gupta I’m not sure what the problem is. The error message seems to say that

sram0

is ok, but shows an error for

sram1

sram2

sram3

. I noticed that the

user_proj_example.v

rtl file include the

sky130_sram_1kbyte_1rw1r_32x256_8

. You probably shouldn’t have that there because it’s supposed to be a blackbox.

Mitch Bailey

02/17/2025, 4:39 AM

Also the power connections in the sram instances are empty.

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`ifdef USE_POWER_PINS
        .vccd1(),
        .vssd1(),
`endif

Can you try changing this to

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`ifdef USE_POWER_PINS
        .vccd1(vccd1),
        .vssd1(vssd1),
`endif

Sanchit Gupta

02/17/2025, 9:35 AM

i have removed sky130_sram_1kbyte_1rw1r_32x256_8 module from user_proj_example.v file and also have added power connections in sram instances, but still same error is there.

Mitch Bailey

02/17/2025, 11:39 AM

@Sanchit Gupta huh. Can you reshare the

config.json

macro_placement.cfg

, and

verilog/rtl/user_proj_example.v

files? It looks like sram files have been copied to the

verilog/rtl/files

directory. You can use this syntax to access the files directly from the pdk

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pdk_dir::libs.ref/sky130_sram_macros/lef/sky130_sram_2kbyte_1rw1r_32x512_8.lef

Sanchit Gupta

02/17/2025, 12:15 PM

yes, i have added all SRAM files in a new diectory.

macro_placement.cfg config.json user_proj_example.v

Mitch Bailey

02/17/2025, 1:18 PM

I still see this line in the

user_proj_example.v

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module sky130_sram_1kbyte_1rw1r_32x256_8(

I would not put this module in the

user_proj_example.v

file, but instead include it in the configuration. I don’t know if this is what is causing the problem or not. Can you try this

config.json

file? Note that I’ve also changed the clock to

clk0

since

demo_top.clk

doesn’t exist.

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{
  "DESIGN_NAME": "user_proj_example",
  "DESIGN_IS_CORE": 0,
  "VERILOG_FILES": [
    "dir::../../verilog/rtl/defines.v",
    "pdk_dir::libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v",
    "dir::../../verilog/rtl/user_proj_example.v"
  ],
  "VERILOG_FILES_BLACKBOX": [
    "pdk_dir::libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v"
  ],
  "CLOCK_PERIOD": 20,
  "CLOCK_PORT": "wb_clk_i",
  "CLOCK_NET": "clk0",
  "FP_SIZING": "absolute",
  "DIE_AREA": "0 0 2850 3320",
  "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
  "FP_PDN_MACRO_HOOKS": "sram0 vccd1 vssd1 vccd1 vssd1, sram1 vccd1 vssd1 vccd1 vssd1, sram2 vccd1 vssd1 vccd1 vssd1, sram3 vccd1 vssd1 vccd1 vssd1",
  "MACRO_PLACEMENT_CFG": "dir::macro_placement.cfg",
  "EXTRA_LEFS": "pdk_dir::libs.ref/sky130_sram_macros/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef",
  "EXTRA_GDS_FILES": "pdk_dir::libs.ref/sky130_sram_macros/gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds",
  "EXTRA_LIBS": "pdk_dir::libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib",
  "PL_BASIC_PLACEMENT": 0,
  "PL_TARGET_DENSITY": 0.42,
  "VDD_NETS": [
    "vccd1"
  ],
  "GND_NETS": [
    "vssd1"
  ],
  "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
  "DIODE_INSERTION_STRATEGY": 3,
  "RUN_CVC": 1,
  "RUN_KLAYOUT_XOR": false,
  "MAGIC_DRC_USE_GDS": false,
  "QUIT_ON_MAGIC_DRC": false,
  "pdk::sky130*": {
    "FP_CORE_UTIL": 45,
    "RT_MAX_LAYER": "met4",
    "scl::sky130_fd_sc_hd": {
      "CLOCK_PERIOD": 20
    },
    "scl::sky130_fd_sc_hdll": {
      "CLOCK_PERIOD": 10
    },
    "scl::sky130_fd_sc_hs": {
      "CLOCK_PERIOD": 8
    },
    "scl::sky130_fd_sc_ls": {
      "CLOCK_PERIOD": 10,
      "SYNTH_MAX_FANOUT": 5
    },
    "scl::sky130_fd_sc_ms": {
      "CLOCK_PERIOD": 10
    }
  },
  "pdk::gf180mcuC": {
    "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
    "CLOCK_PERIOD": 24,
    "FP_CORE_UTIL": 40,
    "RT_MAX_LAYER": "Metal4",
    "SYNTH_MAX_FANOUT": 4,
    "PL_TARGET_DENSITY": 0.45
  }
}

Sanchit Gupta

02/17/2025, 1:48 PM

sorry, by mistake i have uploaded same user_proj_example file in which sky130_sram_1kbyte_1rw1r_32x256_8 module is present. i will try this config file.

Mitch Bailey

02/19/2025, 4:16 AM

@Sanchit Gupta Did that help solve the problem?

Sanchit Gupta

02/20/2025, 7:03 AM

@Mitch Bailey Sorry for the late reply—I was sick for the last 2 days. I've now checked the config file, and I'm getting an error in step 2.

Mitch Bailey

02/20/2025, 1:04 PM

Could you reshare the

config.json

file?

👍 1

Sanchit Gupta

02/20/2025, 2:13 PM

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{
  "DESIGN_NAME": "user_proj_example",
  "DESIGN_IS_CORE": 0,
  "VERILOG_FILES": [
    "dir::../../verilog/rtl/defines.v",
    "pdk_dir::libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v",
    "dir::../../verilog/rtl/user_proj_example.v"
  ],
  "VERILOG_FILES_BLACKBOX": [
    "pdk_dir::libs.ref/sky130_sram_macros/verilog/sky130_sram_2kbyte_1rw1r_32x512_8.v"
  ],
  "CLOCK_PERIOD": 20,
  "CLOCK_PORT": "wb_clk_i",
  "CLOCK_NET": "clk0",
  "FP_SIZING": "absolute",
  "DIE_AREA": "0 0 2850 3320",
  "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
  "FP_PDN_MACRO_HOOKS": "sram0 vccd1 vssd1 vccd1 vssd1, sram1 vccd1 vssd1 vccd1 vssd1, sram2 vccd1 vssd1 vccd1 vssd1, sram3 vccd1 vssd1 vccd1 vssd1",
  "MACRO_PLACEMENT_CFG": "dir::macro_placement.cfg",
  "EXTRA_LEFS": "pdk_dir::libs.ref/sky130_sram_macros/lef/sky130_sram_1kbyte_1rw1r_32x256_8.lef",
  "EXTRA_GDS_FILES": "pdk_dir::libs.ref/sky130_sram_macros/gds/sky130_sram_1kbyte_1rw1r_32x256_8.gds",
  "EXTRA_LIBS": "pdk_dir::libs.ref/sky130_sram_macros/lib/sky130_sram_1kbyte_1rw1r_32x256_8_TT_1p8V_25C.lib",
  "PL_BASIC_PLACEMENT": 0,
  "PL_TARGET_DENSITY": 0.42,
  "VDD_NETS": [
    "vccd1"
  ],
  "GND_NETS": [
    "vssd1"
  ],
  "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
  "DIODE_INSERTION_STRATEGY": 3,
  "RUN_CVC": 1,
  "RUN_KLAYOUT_XOR": false,
  "MAGIC_DRC_USE_GDS": false,
  "QUIT_ON_MAGIC_DRC": false,
  "pdk::sky130*": {
    "FP_CORE_UTIL": 45,
    "RT_MAX_LAYER": "met4",
    "scl::sky130_fd_sc_hd": {
      "CLOCK_PERIOD": 20
    },
    "scl::sky130_fd_sc_hdll": {
      "CLOCK_PERIOD": 10
    },
    "scl::sky130_fd_sc_hs": {
      "CLOCK_PERIOD": 8
    },
    "scl::sky130_fd_sc_ls": {
      "CLOCK_PERIOD": 10,
      "SYNTH_MAX_FANOUT": 5
    },
    "scl::sky130_fd_sc_ms": {
      "CLOCK_PERIOD": 10
    }
  },
  "pdk::gf180mcuC": {
    "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
    "CLOCK_PERIOD": 24,
    "FP_CORE_UTIL": 40,
    "RT_MAX_LAYER": "Metal4",
    "SYNTH_MAX_FANOUT": 4,
    "PL_TARGET_DENSITY": 0.45
  }
}

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