Göktuğ Saray
02/10/2025, 9:01 AMMitch Bailey
02/10/2025, 1:01 PMCircuit 1: uart                            |Circuit 2: uart                            
-------------------------------------------|-------------------------------------------
sky130_fd_sc_hd__decap_3 (213->16)         |sky130_fd_sc_hd__decap_3 (213->1) **Mismat 
sky130_ef_sc_hd__decap_12 (298->14)        |sky130_ef_sc_hd__decap_12 (298->1) **Misma 
sky130_fd_sc_hd__fill_1 (81->1)            |sky130_fd_sc_hd__fill_1 (81->1)            
sky130_fd_sc_hd__tapvpwrvgnd_1 (62->1)     |sky130_fd_sc_hd__tapvpwrvgnd_1 (62->1)     
sky130_fd_sc_hd__buf_2 (10)                |sky130_fd_sc_hd__buf_2 (10)                
sky130_fd_sc_hd__decap_8 (49->2)           |sky130_fd_sc_hd__decap_8 (49->1) **Mismatc
The parallel reduction of decap cells in the layout (left) should go to one just like the source netlist (right).Mitch Bailey
02/10/2025, 1:05 PMNet: output9/VPB                           |(no matching net)                          
  sky130_fd_sc_hd__buf_2/VPB = 4           |                                           
  sky130_fd_sc_hd__decap_3/VPB = 1         |                                           
  sky130_fd_sc_hd__decap_8/VPB = 1         |
The power to the output9 instance is not connected to the vdda1 power rail.
Incidentally, what voltage are you applying to vdda1? I hope it’s not 3.3V because all those standard cells have thin-ox 1.8V devices.Göktuğ Saray
02/10/2025, 2:36 PMMitch Bailey
02/10/2025, 4:45 PMGöktuğ Saray
02/10/2025, 6:05 PMGöktuğ Saray
02/10/2025, 6:52 PMGöktuğ Saray
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