Hello, I am having issues with precheck LVS, it is the only test that is failing when I run precheck and I don't know why. These are the files associated with the LVS check. The main concern I have is that there is no /outputs/reports/lvs.report which would be super helpful to figure out what is wrong with the LVS, and I dont know why it isn't being created. Nonetheless, I will also include the comp.out file from the netgen LVS

Hey @Travis Jakl. The LVS in precheck is designed to handle a wide variety of use cases. Please be sure that the

lvs/user_analog_project_wrapper/lvs_config.json

corresponds to your design environment. 1. From the log file attached, you can see that the PDK versions do not match.

WARNING: Tech files do not match:
/home/tjdjakl/reram_crossbar_project/dependencies/pdks/sky130B/libs.tech/magic/sky130B.tech: version 1.0.424-0-g78b7bc3
/home/tjdjakl/mpw_precheck/checks/be_checks//tech/sky130B/sky130B.tech: version 1.0.470-0-g6d4d117
Results may be incorrect. Contact efabless to update the soft connection rules.

Looks like the design pdk is at

1.0.424

but LVS is expecting

1.0.470

. Is it possible to update the pdk (for LVS), possibly with the following command? If you’re using openlane for logic synthesis, then a different pdk may be required.

volare enable 6d4d11780c40b20ee63cc98e645307a9bf2b2ab8

2. Can you share your

lvs/user_analog_project_wrapper/lvs_config.json

file? There’s a log message that says

/home/tjdjakl/reram_crossbar_project/verilog/gl/user_analog_project_wrapper.v: No such file or directory

3. Also the

comp.out

file shows an unexpected

user_analog_project_wrapper_empty

cell. This file is not output of lvs precheck, is it?

Flattening unmatched subcell 2-1MUX in circuit user_analog_project_wrapper (0)(1 instance)
Flattening unmatched subcell x2-1MUX in circuit user_analog_project_wrapper_empty (1)(1 instance)

@Mitch Bailey I just realized the comp.out file I included was the wrong one. However, upon updating the pdk and rerunning precheck, I still get the same issue with lvs.report not showing up

@Travis Jakl What command are you using to run netgen locally? The precheck

lvs_config.json

file contains the following

"$UPRJ_ROOT/verilog/gl/$TOP_SOURCE.v"

Since

TOP_SOURCE

is set to

user_analog_project_wrapper

, the script expects to find

$UPRJ_ROOT/verilog/gl/user_analog_project_wrapper.v

. Does this file exist? If the top level is a spice file, put that file in the

LVS_SPICE_FILES

section.

I am using

netgen lvs "./xschem/file instance_name" "./magic/file instance_name" sky130B_setup.tcl

to run my local netgen lvs check.

The local command is using an xschem spice file, but the

lvs_config.json

file for precheck is set to use a verilog file. See https://open-source-silicon.slack.com/archives/C032Y8J3KHA/p1738572277066969?thread_ts=1738531845.353469&cid=C032Y8J3KHA The local command uses different names for the top layout -

user_analog_project_wrapper

vs

user_analog_project_wrapper_empty

. The top layout must be

user_analog_project_wrapper

and the netlist and layout cell names must match for precheck. There may be other problems because I’m seeing this in the precheck log

Ignoring line starting with token: sky130_fd_pr__nfet_g5v0d10v5_6XHARQ
line number 3 = 'sky130_fd_pr__nfet_g5v0d10v5_6XHARQ a_n108_n75# a_n50_n163# a_n242_n297# a_50_n75#'
Reading netlist file /home/tjdjakl/reram_crossbar_project/precheck_results/04_FEB_2025___17_14_07/tmp/ext/user_analog_project_wrapper.gds.nowell.spice
Call to undefined subcircuit sky130_fd_pr__nfet_g5v0d10v5
Creating placeholder cell definition.
.ENDS occurred outside of a subcircuit!
line number 5 = '.ends'