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42-uart.lef.lvs.log

config.json

Hello, I am currently learning OpenLane and i wanted to run a uart module through the flow. This uart has 3 hardened blocks inside; baud_rate_gen, receiver and transmitter respectively. I can succesfully run the flow for each macro but on the chip level integration I am getting an LVS error. My guess is that there is something wrong with the PDN as on gui I see that some Power lines do not meet but I have no idea how to fix this. I attached necessary files and would appericiate any help. It is important to note that I was following the *Hierarchical chip design(with macros)* tutorial from the docs page.

<@U07T59NPKCJ> Looks like you might have some narrow cell rows that aren’t connected to power.
```Circuit 1: uart                            |Circuit 2: uart                            
-------------------------------------------|-------------------------------------------
sky130_fd_sc_hd__decap_3 (213-&gt;16)         |sky130_fd_sc_hd__decap_3 (213-&gt;1) **Mismat 
sky130_ef_sc_hd__decap_12 (298-&gt;14)        |sky130_ef_sc_hd__decap_12 (298-&gt;1) **Misma 
sky130_fd_sc_hd__fill_1 (81-&gt;1)            |sky130_fd_sc_hd__fill_1 (81-&gt;1)            
sky130_fd_sc_hd__tapvpwrvgnd_1 (62-&gt;1)     |sky130_fd_sc_hd__tapvpwrvgnd_1 (62-&gt;1)     
sky130_fd_sc_hd__buf_2 (10)                |sky130_fd_sc_hd__buf_2 (10)                
sky130_fd_sc_hd__decap_8 (49-&gt;2)           |sky130_fd_sc_hd__decap_8 (49-&gt;1) **Mismatc ```
The parallel reduction of decap cells in the layout (left) should go to one just like the source netlist (right).

This one should be easy to check.
```Net: output9/VPB                           |(no matching net)                          
  sky130_fd_sc_hd__buf_2/VPB = 4           |                                           
  sky130_fd_sc_hd__decap_3/VPB = 1         |                                           
  sky130_fd_sc_hd__decap_8/VPB = 1         |                                           ```
The power to the `output9` instance is not connected to the vdda1 power rail.

Incidentally, what voltage are you applying to `vdda1`? I hope it’s not 3.3V because all those standard cells have thin-ox 1.8V devices.

I cant find any way to specify the applied voltage on the tool. How can i do this?

I suppose you could set it in you spice simulation but the voltage level is not important for LVS. It is important if you want your actual design to work, but that’s a different issue. What voltage were you planning for vdda1? From 1.8V to 5.0V are supported by the caravel framework.

For now the voltage level is not important to me honestly as I am only trying to understand the tool and pass some designs through the flow. I understand the points you provided that are not connected to power but i am not certain how i can fix it. I am not going to be using caravel either for now so this will be a standalone design.

44-uart.lef.lvs.log

I added vdda1 along with vccd1 to the design and ran it again. This time it seemed to have improved. It seems there only a mismatch now in the vdda1 and vssa1 line of the uart circuit.  I attached the configuration and log file. What can i do to fix the mismatch at this point?

I removed the vdda1 and vssa1 and kept only vccd1 and vssd1 and the problem was fixed. I initially used vdda1 and vssd1 as only power and gnd nets. Apparently this was wrong.