Hello, About the Vdda1-2/vssa1-2/vdda1-2/vssa1-2, are they essentially bare pads connected to the user area or are there circuits in between (ESD, buffers, etc)? I am trying to determine what parasitics may be on those pads if I were to try to use them for high frequency design biases. Thanks!

They are proper power pads with clamp circuits connected to them. However, I have anticipated your need. What you are looking for is the "caravan" chip variant of caravel (see the #C02096M650E channel). The caravan chip replaces 11 of the GPIO cells across the top of the chip with bare pads, really just bare pads with no ESD. You are responsible for either adding ESD structures or else handling the chip very carefully. The bare pads have been used in the past for running signals of 2GHz+. I do not have a measurement of what the actual bandwidth of these pads is, but I would guess it's around 3GHz or so.

Thank you! I must have posted in the wrong channel, I am planning on using caravan but am running out of bare pads, and I was wondering if the vdd/vsss pins would be suitable for some of the chip biasing. Do you know where I could find more information on the clamp circuits/other things attached to those pins?

Some of it you will find here: https://skywater-pdk.readthedocs.io/en/main/contents/libraries/sky130_fd_io/docs/user_guide.html#usage-of-outer-guard-rin[…]-clamps-for-sky130-fd-io However, since the I/O cells themselves do not make connections to the clamps, you also have to refer to the Caravel documentation about which clamps are connected to which pads, which is here: https://github.com/efabless/caravel/blob/main/docs/source/_static/voltage_clamp_arrangement.svg In all cases of the caravel/caravan pad frame, 1.8V domain (vccd/vssd) pads are connected to low voltage clamps, and 3.3V domain (vdda/vssa) pads are connected to high voltage clamps.