Hi
@Wajid Malik, in both Caravel and Caravel Mini, the CPU is always the master of the SoC's Wishbone bus. This is evidenced by
the key Wishbone signals into the user project area all being defined as `input`s only. While you could implement a Wishbone master in your user project, and optionally mux it with the Caravel Wishbone master signals that come into the user project, it would only allow you to control your own devices inside the user project and not take over the Caravel/SoC peripherals.