open-source-silicon.dev

Hello <@U01QTMG2K8R>, for three R2R DACs, when I set one to high, two to high, and three to 0 input, I can see that the output of 2 DAC is experiencing an inverted voltage drop. Can anyone please help me?

When I keep all three DACs set to high, the output is correct. However, when I try setting different input values, there is a voltage drop.

Try your RDAC without a load first. No level shifter at the output.

<@U01QTMG2K8R> hi its working correct without the load but idk what is happening when i connect level shifter at output

I just see some noisy signals for net names I don't have any clue what they mean. If you say it works, it works.

The problem is that your RDAC is not buffered, so it can't provide the current for you level shifters.

When I added a capacitor to the output, the noise was reduced, and the signal from the DAC became smoother. However, when I connected it to the level shifter, the signal was low.

Try connecting a vcvs source as an ideal buffer between the RDAC and the level shifters.

so i should keep capacitor or remove while adding ideal buffer

It doesn't matter. You should run a transient sim with binary input signals and see a staircase if you sweep all the inputs. It's not what you're doing right now.

Generally, an opamp is needed in a R2R DAC. Otherwise, the output impedance is high. That reduces the drive strength of the DAC

<@U028DBG5NA1>  i used buffer so compare to buffer and opamp what will be good ? 

But using buffer is causing the output variation in levelshifter and dac output is correct

Hello <@U01QTMG2K8R> Luis Henrique Rodovalho, I'm observing a voltage drop in the level shifter output when using a buffer, possibly due to the shorter delay compared to the RC network I've implemented (using a 1µF capacitor and a 500Ω resistor).  At 0V input, I'm seeing a 400nV offset in DAC, likely caused by the capacitor's slower discharge. To address this, I'm considering a multi-stage buffer to increase the delay for level shifter output and achieve a cleaner 0V output. If that's unsuccessful, would a tri-state buffer be a necessary next step?

You need a LDO. uF are unfeasible. Try less than 100 pF. Voltage drops are a fact of life for digital signals and buffered pulse signals.

Just curious why can't we use multi or tri state buffer 

Also from dac I am generating 200mv to 4.3v for level shifter voltage supply in order to change the amplitude and 0v 

Lesser than pf if you're referring to capacitor in RC network at output of DAC it's making way hard to achieve the desire amplitude height compared to uf at output of level shifter and if you're referring in LDO I have to check

You can't make a single level shifter operate at this range of supply voltages. You will need to implement a high speed DAC directly.

Okay thank you 

I will study about high speed DAC 

currently was using R2RDAC