@Tim Edwards I'm getting an LVS mismatch from netgen that I'm not sure is correct. I have some parametric sub-circuits and netgen seems to pick the wrong value during the compare operation (it looks like it's using the default value instead of the adjusted value from the higher up level). See attached for the comp.out, my comparison script, and the schematic and layout netlists. The compaint seems to be that my resistors are 12um long in layout and 10um long in the schematic, but at the toplevel the schematic shows 12um too. Or am I missing something here?

Netgen's SPICE parser is supposed to deal with such parameters being passed down the subcircuit hierarchy. I agree with your assessment, though, and will have to figure out why that did not happen. I am sure that I have tested parameter passing before.

Ok, thanks, I'll bypass it for now by setting the default to the actual value as that seems to 'fix' the issue for now

I recall the history of dealing with the issue; the main problem is that netgen compares hierarchically from bottom to top. By having a parameterized schematic cell, you're effectively creating one schematic cell that can potentially match an arbitrary number of different layout cells. One solution that comes to mind is just to flatten that cell, although I tried that and it appears that netgen doesn't know how to substitute subcircuit parameters when flattening (although I don't think that would be particularly difficult to implement). A "proper" solution would require netgen to duplicate the schematic circuit and do a lot of bookkeeping to keep track of the hierarchy, and which instances use which parameters.

ok, good to know, thanks for having a look at it!