Hi folks, I have a more general question regarding hierarchical STA\SDF. In the Caravel flow we have wires from driver sources in macros via the top level to targets in macros. We have a wrapper SDF file. I know that so far hierarchical STA is not supported. So just in general: Question 1: The delays in the wrapper SDF file, do they only cover the segments on wrapper level? And if so, don’t they depend on the driver and cap in the source macro and the cap in the target macro as well? How is that handled ? Question 2: Are hierarchical SDF\STA flows known by now to be accurate on industrial level ? (I think we skipped it at LSI Logic in 1999 as we decided that this is not practicable). Thank you for your answer in advance. Cheers, Tobias