Zineddine Haboussi
01/08/2025, 12:11 AMMitch Bailey
01/08/2025, 1:50 AM.lib
files are might be used for timing/power estimates at the gate level (verilog). I don’t know that there is timing/power information at the discrete device level.
Do you mean the spice models for nfet_01v8
? If so, you can find them here $PDK_ROOT/$PDK/libs.ref/sky130_fd_pr/spice
.