is there a document on the management VexRISC core , like its registers and so...

SoC: https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/ Not sure about the vexriscv configuration in terms of RISC-V extensions

Like what's exactly inside the core - ALU, general purpose register, special registers ,PC, SP etc... I was about to write a code in assembly , so in order to further move forward I need to know the registers and so...

It's a 32-bit RISC-V processor. For example, whether it does or doesn't support the div instruction depends on whether it has the D extension, which as I said, isn't clear to me from docs.

As per makefile and other docs its rv32i_zicsr

Good, then from that you already know what architectural registers are available

Sir could you please elaborate it , I'm a bit confused. As per the extensions it doesnt natively support floating point, multiply and divide. I believe which is why the soft float throwed up error while linking with the project.

As I pointed out in the other thread, gcc emmits soft float and integer multiplication and division functions into your code or it should be in the appropriate libgcc.a in your RISC-V toolchain so as long as you link that into your program you should have access to those