Hi, I'm trying to do a simple push through the car...
# caravel
a
Hi, I'm trying to do a simple push through the caravel flow by connecting a verilog-based encoder with a decoder created using virtuoso using SKY130. I'm failing this step in when making the user project wrapper, and I'm not sure how to debug it since the decoder passed LVS through virtuoso. Any ideas?
👀 1
m
@AV looks like the macro power might not be connected. Can you share your
config.json
file and the
logs/signoff/39-user_project_wrapper.lef.lvs.log
?
a
m
@AV I think you need a line like this in your
config.json
file.
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"FP_PDN_MACRO_HOOKS": "<decoder> vccd1 vssd1 VDD <GND>",
replace
<decoder>
with the verilog decoder instance name and replace
<GND>
with the decoder ground net name.
This should work
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"FP_PDN_MACRO_HOOKS": "dec vccd1 vssd1 VDD GND",
However, I also see this in the log file
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Warning: Equate pins:  cell decoder is a placeholder, treated as a black box.

Subcircuit pins:
Circuit 1: decoder                         |Circuit 2: decoder                         
-------------------------------------------|-------------------------------------------
VDD                                        |VDD                                        
GND                                        |GND                                        
A                                          |(no matching pin)                          
B                                          |(no matching pin)                          
Y0                                         |(no matching pin)                          
Y1                                         |(no matching pin)                          
Y2                                         |(no matching pin)                          
Y3                                         |(no matching pin)                          
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes decoder and decoder are equivalent.
Which seems to indicate that the verilog for decoder is missing.
a
As I was trying to fix this, I'm seeing this new error at Step 23 (Running Detailed Routing) and the log file contains a lot of warnings saying:
[WARNING DRT-6000] Macro pin has more than 1 polygon
. Would you know what could be wrong?
m
@AV I’m guessing that the lef file for the macro isn’t what openlane is expecting. Can you open the lef file in klayout and check the pin shapes?
a
Tried that... I'm still stuck at that step... Here's a screenshot of the error and the detailed.log file:
I tried running my added design through KLayout and it passes drc so I'm not sure why it's failing here
m
@AV looking at the log file, it’s stopping after the 64th iteration with 3 mcon violations. Looks like these violations are occurring from the 6th iteration and never making any progress. It may be due to off-grid ports on the macro or ports that are too close. I’d suggest not using minimum spacing on the macro ports. Can you look at the routing to the macro ports to see any congestion?
Can you share your decoder layout?
a
decoder.gds
m
@AV After looking at the macro, I’m thinking that the problem might be with the routing grid not aligning with the macro ports. Can you look at the last detail routed layout? if there’s not a gds file available then there’s probably an odb file in one of the temporary directories under
runs/<timestamp>
. Try using
openroad -gui
to open the odb file. Looking at the lef file for decoder might help. Can you share that?
a
The detailed routing step actually ends up failing... So I don't think it generates an odb file
decoder.lef
m
The lef file looks a little different than the gds file. For one, it’s about twice as wide. Also the metal1 input pins look much bigger in the lef than in the gds. How did you create the lef file?
a
I used "lef write" on magic
m
@AV try setting a cell boundary with
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load decoder
select top cell
property FIXED_BBOX [view bbox]
lef write -pinonly
I’m not sure what this will produce, but you should be able to open the lef file in klayout to check that It looks reasonable.