AV
12/07/2024, 9:50 PMMitch Bailey
12/07/2024, 9:57 PMconfig.json
file and the logs/signoff/39-user_project_wrapper.lef.lvs.log
?AV
12/07/2024, 10:27 PMMitch Bailey
12/08/2024, 11:08 AMconfig.json
file.
"FP_PDN_MACRO_HOOKS": "<decoder> vccd1 vssd1 VDD <GND>",
replace <decoder>
with the verilog decoder instance name and replace <GND>
with the decoder ground net name.Mitch Bailey
12/08/2024, 11:58 AM"FP_PDN_MACRO_HOOKS": "dec vccd1 vssd1 VDD GND",
However, I also see this in the log file
Warning: Equate pins: cell decoder is a placeholder, treated as a black box.
Subcircuit pins:
Circuit 1: decoder |Circuit 2: decoder
-------------------------------------------|-------------------------------------------
VDD |VDD
GND |GND
A |(no matching pin)
B |(no matching pin)
Y0 |(no matching pin)
Y1 |(no matching pin)
Y2 |(no matching pin)
Y3 |(no matching pin)
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes decoder and decoder are equivalent.
Which seems to indicate that the verilog for decoder is missing.AV
12/09/2024, 2:15 AM[WARNING DRT-6000] Macro pin has more than 1 polygon
. Would you know what could be wrong?Mitch Bailey
12/09/2024, 2:41 AMAV
12/11/2024, 11:35 PMAV
12/11/2024, 11:35 PMMitch Bailey
12/12/2024, 1:30 AMMitch Bailey
12/12/2024, 1:31 AMAV
12/12/2024, 1:32 AMMitch Bailey
12/12/2024, 2:31 AMruns/<timestamp>
. Try using openroad -gui
to open the odb file.
Looking at the lef file for decoder might help. Can you share that?AV
12/12/2024, 2:35 AMAV
12/12/2024, 2:35 AMMitch Bailey
12/12/2024, 4:19 AMAV
12/12/2024, 4:40 AMMitch Bailey
12/12/2024, 4:49 AMload decoder
select top cell
property FIXED_BBOX [view bbox]
lef write -pinonly
I’m not sure what this will produce, but you should be able to open the lef file in klayout to check that It looks reasonable.