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Hi everyone. We are currently getting into LVS err...
# lvs
a
Hi everyone. We are currently getting into LVS errors mostly with user porject wrapper pins. We tried a bunch of stuff but nothing helped. Does anyone have any idea why this is happening? I am also adding the link to my github repo incase anyone wants to see the design fles. https://github.com/Asma-Mohsin/open_eFPGA
40-user_project_wrapper.lef.lvs.log40-user_project_wrapper.lef.lvs.json40-lvs.lef.log
m
@Asma Mohsin the block counts match, but the layout has almost 189 more nets than the source.
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Number of devices: 10917                   |Number of devices: 10917                  
Number of nets: 39818 **Mismatch**         |Number of nets: 39629 **Mismatch**
The fun part is trying to figure out what those are. Scrolling through the very long list, it looks like there are some unconnected macros with unconnected power: 
LUT4AB
, 
N_term_single2
, 
sky130_sram_1kbyte_1rw1r_32x256_8
, 
S_term_single2
, 
S_term_DSP
, 
N_term_DSP
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Net: eFPGA_top_i.eFPGA_inst.Tile_X1Y7_LUT4 |Net: _NC48                                
  LUT4AB/vccd1 = 1                         |  sky130_sram_1kbyte_1rw1r_32x256_8/dout0[
                                           |                                          
Net: eFPGA_top_i.eFPGA_inst.Tile_X4Y2_LUT4 |Net: _NC49                                
  LUT4AB/vssd1 = 1                         |  sky130_sram_1kbyte_1rw1r_32x256_8/dout0[
                                           |
…
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Net: eFPGA_top_i.eFPGA_inst.Tile_X3Y0_N_te |Net: _noconnect_102_
  N_term_single2/vccd1 = 1                 |  sky130_fd_sc_hd__conb_1/HI = 1
                                           |
Net: eFPGA_top_i.eFPGA_inst.Tile_X3Y0_N_te |Net: _noconnect_103_
  N_term_single2/vssd1 = 1                 |  sky130_fd_sc_hd__conb_1/HI = 1
                                           |
…
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Net: eFPGA_top_i.Inst_BlockRAM_3.memory_ce |Net: \eFPGA_top_i.eFPGA_inst.Tile_X5Y0_Fra
  sky130_sram_1kbyte_1rw1r_32x256_8/vccd1  |  N_term_single/FrameStrobe_O[14] = 1     
                                           |                                          
...

Net: eFPGA_top_i.Inst_BlockRAM_0.memory_ce |Net: \eFPGA_top_i.eFPGA_inst.Tile_X5Y0_Fra
  sky130_sram_1kbyte_1rw1r_32x256_8/vssd1  |  N_term_single/FrameStrobe_O[13] = 1
…
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Net: eFPGA_top_i.eFPGA_inst.Tile_X3Y13_S_t |Net: _noconnect_193_                      
  S_term_single2/vssd1 = 1                 |  sky130_fd_sc_hd__conb_1/LO = 1          
...
Net: eFPGA_top_i.eFPGA_inst.Tile_X3Y13_S_t |Net: _noconnect_80_                       
  S_term_single2/vccd1 = 1                 |  sky130_fd_sc_hd__conb_1/HI = 1
…
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Net: eFPGA_top_i.eFPGA_inst.Tile_X6Y13_S_t |Net: _noconnect_31_                       
  S_term_DSP/vccd1 = 1                     |  sky130_fd_sc_hd__conb_1/HI = 1          
                                           |                         
Net: eFPGA_top_i.eFPGA_inst.Tile_X6Y13_S_t |Net: _noconnect_32_                       
  S_term_DSP/vssd1 = 1                     |  sky130_fd_sc_hd__conb_1/HI = 1
…
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Net: eFPGA_top_i.eFPGA_inst.Tile_X6Y0_N_te |(no matching net)                         
  N_term_DSP/vccd1 = 1                     |                                          
                                           |                         
Net: eFPGA_top_i.eFPGA_inst.Tile_X6Y0_N_te |(no matching net)                         
  N_term_DSP/vssd1 = 1                     |
a
Thanks @Mitch Bailey . we solved this with that comma in FP_PDN_MACRO_HOOKS. however we still have mismatches in the top wrapper pins.
👍 1
Dumb question: How did u figure out what was causing the error?
i could see alot of no matching net so how exactly do you know whats the issue?
39-user_project_wrapper.lef.lvs.log
39-user_project_wrapper.lef.lvs.log
This is the new lvs with 1 net mismatch and all the pins mismatch. Not sure how u were able to figure out the error.
m
@Asma Mohsin I look for things that are out of place.
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Net: eFPGA_top_i.eFPGA_inst.Tile_X9Y0_N_te |(no matching net)
  N_term_RAM_IO/VPWR = 1                   |
Is this assigned in the 
FP_PDN_HOOKS
?
👍 1
a
Yup I also saw that. it wasnt.
👍 1
not changed its position to connect this macro to power. the flow is still on run.
Will let u know the outcome
👍 1
@Mitch Bailey LVS passed. Thankyou soo much
👍 1
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