Hi, I'm trying to do a simple push through the car...
# caravel
a
Hi, I'm trying to do a simple push through the caravel flow by connecting an encoder with a decoder. In my
user_project_wrapper.v
file in
verilog/rtl
, here is what I'm doing to connect the two components:
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wire [1:0] enc_out;
encoder enc (
`ifdef USE_POWER_PINS
	.vccd1(vccd1),
	.vssd1(vssd1),
`endif
	.in(io_in[0]),
	.out(enc_out)
);
decoder dec (
`ifdef USE_POWER_PINS
	.vccd1(vccd1),
	.vssd1(vssd1),
`endif
	.A(enc_out),
	.Y(io_out[0])
);
This is causing the following error:
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[ERROR]: during executing sta script /openlane/scripts/openroad/sta/multi_corner.tcl
[ERROR]: Log: logs/synthesis/2-sta.log
[ERROR]: Last 10 lines:
Using 1e-12 for capacitance...
Using 1e+03 for resistance...
Using 1e-09 for time...
Using 1e+00 for voltage...
Using 1e-03 for current...
Using 1e-09 for power...
Using 1e-06 for distance...
Reading netlist 'project/openlane/user_project_wrapper/runs/24_12_03_23_14/results/synthesis/user_project_wrapper.v'…
Error: project/openlane/user_project_wrapper/runs/24_12_03_23_14/results/synthesis/user_project_wrapper.v line 4, syntax error, unexpected REG
child process exited abnormally
Could anyone explain how I can go about fixing this?
a
Can you send your user_project_wrapper.v?
a
user_project_wrapper.v
a
Quick question: Are these dec and enc macros or simple verilog?
if they are not macros, dont put this ifdef use_power_pins
👍 1
also send ur synthesis.log and project/openlane/user_project_wrapper/runs/24_12_03_23_14/results/synthesis/user_project_wrapper.v if possible
a
user_project_wrapper.v,1-synthesis.log
a
Do you have a github repo that u can share so we can try this at our end?
m
Unrelated question: You are using io[0] for both modules, the input for the encoder and the output for the decoder. Are you making sure that just either the encode or the decoder is used at the same time? Also make sure to set the oeb to the desired value, depending on if you are using the input (oeb=1) or output (oeb=0). Also you should probably remove the user_proj_example module if you are creating your own design.
a
@Asma Mohsin I don't have this in a github repo... would you like me to send you the relevant project files? @Marcel Jung Thanks for catching that-- it was a typo. I'll also be sure to set the oeb.
a
Yes sure. Send the files.