AV
12/05/2024, 4:52 PMuser_project_wrapper.v
file in verilog/rtl
, here is what I'm doing to connect the two components:
wire [1:0] enc_out;
encoder enc (
`ifdef USE_POWER_PINS
.vccd1(vccd1),
.vssd1(vssd1),
`endif
.in(io_in[0]),
.out(enc_out)
);
decoder dec (
`ifdef USE_POWER_PINS
.vccd1(vccd1),
.vssd1(vssd1),
`endif
.A(enc_out),
.Y(io_out[0])
);
This is causing the following error:
[ERROR]: during executing sta script /openlane/scripts/openroad/sta/multi_corner.tcl
[ERROR]: Log: logs/synthesis/2-sta.log
[ERROR]: Last 10 lines:
Using 1e-12 for capacitance...
Using 1e+03 for resistance...
Using 1e-09 for time...
Using 1e+00 for voltage...
Using 1e-03 for current...
Using 1e-09 for power...
Using 1e-06 for distance...
Reading netlist 'project/openlane/user_project_wrapper/runs/24_12_03_23_14/results/synthesis/user_project_wrapper.v'…
Error: project/openlane/user_project_wrapper/runs/24_12_03_23_14/results/synthesis/user_project_wrapper.v line 4, syntax error, unexpected REG
child process exited abnormally
Could anyone explain how I can go about fixing this?Asma Mohsin
12/05/2024, 4:56 PMAV
12/05/2024, 4:57 PMAsma Mohsin
12/05/2024, 4:58 PMAsma Mohsin
12/05/2024, 5:00 PMAsma Mohsin
12/05/2024, 5:01 PMAV
12/05/2024, 5:06 PMAsma Mohsin
12/05/2024, 5:08 PMMarcel Jung
12/05/2024, 5:08 PMAV
12/05/2024, 6:32 PMAsma Mohsin
12/05/2024, 6:33 PM