Hey everyone. Can someone tell me the command to g...
# analog-designa
Asma Mohsin
12/05/2024, 10:50 AMHey everyone. Can someone tell me the command to generate lib files using gds in magic?
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tnt
12/05/2024, 10:54 AMlib as in liberty file ?
tnt
12/05/2024, 10:54 AMThere is no such thing in magic.
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Asma Mohsin
12/05/2024, 10:55 AMokay then how do it? We have designed an analog IP using magic and want to extract lib files to integrate our IP in a digital design using openlane
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tnt
12/05/2024, 10:56 AMThere is no automated flow.
tnt
12/05/2024, 10:57 AMWhat does that analog IP do ? Do you want timing info integration for it ? Or just not throw an error when integrating it ?
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Asma Mohsin
12/05/2024, 10:58 AMIts an SRAM cell for configuration in FPGA.
Asma Mohsin
12/05/2024, 10:59 AMI actually want the timing info
Asma Mohsin
12/05/2024, 10:59 AMHow do people do it then if there is no automated flow?
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tnt
12/05/2024, 10:59 AMThen you have to create a bunch of SPICE test bench that test how your IP reacts to whatever stimuli you want caracterized and logs / measures all the values for whatever output load and input slew and for all the timing path.
And then from that ... write a liberty file for it.
tnt
12/05/2024, 11:04 AMAs for "how people do it" ...
• I'm assuming commercial tools have helpers or utility to ease the process. But I never used any commercial tools so I don't know for sure
• I think a lot of people just treat their analog IP as "asynchronous" to the digital part and so don't bother with timing.
• And the third option is like I described above, but from what I've seen it's always a ad-hoc solution make specifically for a project. You can have a look in OpenSRAM, maybe they have something that can help you there.
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Asma Mohsin
12/05/2024, 11:10 AMOh okay. Get you now. Thankyou soo much. That was really helpful
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Leo Moser
12/05/2024, 1:15 PMFYI for CMOS standard cells there's lctime: https://codeberg.org/librecell/lctime
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tnt
12/05/2024, 1:29 PM@Leo Moser Oh, nice, I didn't know about it 👍
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Leo Moser
12/05/2024, 1:32 PMYeah, I'm trying to use it with my simple standard cells for the ICPS PDK 😁
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Austin Rovinski
12/06/2024, 7:49 PMYes, library characterization is a common task and there are tools to automate it. The general process @tnt outlined is correct. Characterization requires running a bunch of SPICE simulations and sweeps at various characterization points for the design.
The best tools for this are probably going to be Cadence Liberate or Synopsys PrimeLib, but those are commercial solutions. In the open-source realm, I am not sure that there are feature-complete or heavily validated solutions to do this. CharLib from Oklahoma State might be the place to start, but I'm not sure if it will do SRAMs well. You can possibly look to OpenRAM to see how they do characterization. lctime mentioned above is new to me, but it looks promising.
Austin Rovinski
12/06/2024, 7:51 PMDo note that characterization is still a very manual process because it often requires specific details to be provided on how each terminal is classified and expected to work. The automated part is not having to run 10k SPICE simulations manually.
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