How can I integrate sky130 with cadence tools

Hi @Jnanapurushothama. Yes, the sky130 data is open source and can be installed in a PDK compatible with Cadence. But, the PDKs in open_pdks and volare are not designed for Cadence. I have heard there is a PDK for Cadence in the community. I know no more than that.

@Jnanapurushothama you might try asking in one of the #cadence-* channels.

You can get a SKY130 PDK from Cadence (via download from their support site).

Is the cadence version charged or free ?

It's free.

Hi, I was looking into the same thing (getting SKY130 to work with Cadence tools) but the only thing I came across was a blog post from Cadence where they say SKY130 will soon be available as part of the teaching kit for their VLSI fundamentals, so I mailed them asking for it. This was over a month ago. I also mailed Skywater themselves asking for the PDK. But I have not heard from them. Could anybody please point me to a webpage? I have been unable to find a download specifically for Cadence......does that mean that the PDK files are same just some changes are needed to set it up with virtuoso suite ? (I am assuming that the files would be different since spectre uses scs files)

I said it above, you can download it from the Cadence support site. It requires login, no public website I can point to.

@Mitch Bailey @Boris Murmann @Tim Edwards If a design is created using Cadence tools and the open-source Sky130 PDK downloaded from support site, can it be submitted to ChipIgnite or Tiny Tapeout shuttles for fabrication? Can the GDS generated from Virtuoso be used for running mandatory pre-checks on open-source tools as required for ChipIgnite and Tiny Tapeout shuttles ?

@vks Someone else will have to speak to TinyTapeout, but it can be submitted to ChipIgnite. All we need is the user_project_wrapper GDS file. It then has to pass the online mpw_precheck and tapeout flows. Do be aware that Skywater has increased the number of manufactory required (MR) rules over the past 9 months or so and we have updated the klayout rules to match. I do not know if the Cadence PDK has been updated to match. Just an FYI that you might have layout corrections once you go through the online flows.

Thanks @David Lindley for clarification. In case there is some discrepancy in Cadence generated gds, I believe it would only be some specific layer related which can be handled in klayout itself without having to modify actual layout in Cadence. I faced such an issue with magic related gds in past and was handled in Klayout directly.

My pleasure, @vks.

Thanks to this thread, I have setup the PDK to work with Virtuoso. But, it seems that it doesn't come with any rule files for parasitic extraction. I can only see DRC and LVS rule files with the PDK. Actually I have an MPW5 tape-out (a charge pump based PLL) which was done using FOSS tools and I have all the files for it except its schematic (the original designers didn't create any xschem schematic). And now before testing the design, I want to know if somehow it would be possible to run post-layout simulations (such as pss and pnoise which can't be done using FOSS tools at the moment) using Cadence tools? If I can't do parasitic extraction in Cadence, for SKY130, then I was thinking of feeding the extracted netlist from MAGIC and creating a testbench that way....are MAGIC's parasitic estimates good?

Results from magic's parasitic extraction are reasonably good, are modeled to match the output of FasterCap within a few percent, and I have had confirmation from a few people that measured results matched magic's estimates within a reasonable margin of error. Characterization of the first Chipalooza test chip will be the first large-scale matching of measured results to extraction estimates, and that work has not yet started (but we do have the chips back). So at the moment I don't have any hard numbers to point you to, just anecdotal reports.