Hello, How can I simulate the SRAM macros provided in the PDK?

There are two types of simulation available: characterization and functional. For functional, a stimulus file should be saved with your output that you can run. For characterization, you need to set the option analytical_delay to false and it will then use spice for simulation. This is very slow. We have a commit in progress to run these on previously generated macros.

The verilog models come with the PDK. One has to use them for RTL as well as GLS simulations/verifications. SRAMs don't have gate level models. So, I am not sure if timing simulation (SDF) is possible with SRAMs in design.

We have .lib files for STA but they aren't very accurate still

STA is static. We need some model for gate level timing simulation. For SOC designs with microprocessors, memory, serial protocols we are not sure if the memory read writes are happening in time.

Yes, this is only for static timing. It would be great to have an SDF. Would you be interested in helping?

Yes. I don't know how to extract gate level verilog from schematics. I guess OpenRAMs have schematics directly. They are not synthesized using pdks. If you have a tool to convert schematics to gate level verilog, let me know.

It has some analog so it doesn't make sense to have gate level. It might be possible to create a lib to SDF converter and just use black box timing

Ok, let me see how to write a lib to SDF converter. Will give it a try.

Yeah, if you focus on the input to output delays of the memory as the SDF arcs, it would work

Great discussion! Thanks