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```shabbarvejlani@f9f3ff12e7e7:/home/cad-user$ pyt...
# openram
s
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shabbarvejlani@f9f3ff12e7e7:/home/cad-user$ python3 $OPENRAM_HOME/openram.py myconfig.py 

|==============================================================================|

|=========                       OpenRAM v1.2.0                       =========|

|=========                                                            =========|

|=========               VLSI Design and Automation Lab               =========|

|=========        Computer Science and Engineering Department         =========|

|=========            University of California Santa Cruz             =========|

|=========                                                            =========|

|=========          Usage help: <mailto:openram-user-group@ucsc.edu|openram-user-group@ucsc.edu>           =========|

|=========        Development help: <mailto:openram-dev-group@ucsc.edu|openram-dev-group@ucsc.edu>        =========|

|=========       Temp dir: /tmp/openram_shabbarvejlani_10_temp/       =========|

|=========                See LICENSE for license info                =========|

|==============================================================================|

** Start: 09/17/2022 23:54:57

Technology: sky130

Total size: 32 bits

Word size: 2

Words: 16

Banks: 1

Write size: None

RW ports: 1

R-only ports: 0

W-only ports: 0

DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).

DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).

Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).

Only generating nominal corner timing.

ERROR: file sram_config.py: line 132: Invalid number of cols including rbl(s): 3. Total cols must be divisible by 2

Traceback (most recent call last):

  File "/openram/compiler/openram.py", line 54, in <module>

    c = sram_config(word_size=OPTS.word_size,

  File "/openram/compiler/modules/sram_config.py", line 44, in __init__

    self.compute_sizes()

  File "/openram/compiler/modules/sram_config.py", line 95, in compute_sizes

    self.recompute_sizes()

  File "/openram/compiler/modules/sram_config.py", line 132, in recompute_sizes

    debug.error("Invalid number of cols including rbl(s): {}. Total cols must be divisible by {}".format(self.num_cols + num_ports + self.num_spare_cols, self.array_col_multiple), -1)

  File "/openram/compiler/debug.py", line 47, in error

    assert return_value == 0

AssertionError
a
I am not aware of why this error is happening, but it might be related: ERROR: file sram_config.py: line 132: Invalid number of cols including rbl(s): 3. Total cols must be divisible by 2
s
yes.. but unsure on how to go further. It looks related to sky130 in some way as the same script works on scn4m_subm
m
There should be example configs for sky130. You need to add an extra row and column because it requires an even number for the single port (and there's an extra for the replica column)
s
Thank you for the clarification. I am unable to find where do we have examples in the OpenRam directory. Are there other files similar to myconfig.py(the file in the top
m
https://github.com/VLSIDA/OpenRAM#basic-usage "To run designs in Docker, it is suggested to use, for example: cd openram/macros make example_config_scn4m_subm"
There's a config directory with all of the macro examples
s
thanks a lot, able to run sky130 examples! though the script ends with a drc warning for sky130_sram_2kbyte_1rw_32x512_8: WARNING: file magic.py: line 246: DRC Errors sky130_sram_2kbyte_1rw_32x512_8 271, is it okay to ignore?
m
There are sometimes a few errors that need to be fixed by hand.
s
thanks for confirming
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