occur lvs mismatch during precheck, is anyone can ...
# chipignite
l
occur lvs mismatch during precheck, is anyone can help to point out where can i find the detailed error info ?
t
Netgen is reporting a pin mismatch only, so the output from netgen should be pretty short. Can you post the LVS log file?
l
image.png
yes, lef.log show that there is power pin mismatch. by the way, we are using innovus to do the rtl to gds flow, Is there anything special to consider?
here is the full log.
t
@luping.cui: You can try the most recent version of netgen, since I added some code from Mitch Bailey that makes the pin matching output easier to understand.
l
OK
thanks, i'll have a try