Hi , i am back with sort of same issue. I have two always blocks : one with posedge clk and one with negedge clock , inside which i am assigning diff values : always @(negedge clk) begin if ( is_read_ins ) begin #2 a <= 1; b <= 1 ; c <= 0 ; end end always @(posedge clk) begin if ( is_read_ins ) begin #2 a <= 0; b <= 0 ; c <= 1 ; end end Yosys complains of multi drivers : But logically i can have signals driven by two diff clock edges to two diff values : how am i supposed to model this code ?? Seems logical that I CAN have two signals being assigned two diff values in two clock edges!! Warning: multiple conflicting drivers for a port Q[0] of cell $procdff$12172 ($dff) port Q[0] of cell $procdff$12180 ($dff) Warning: multiple conflicting drivers for b port Q[0] of cell $procdff$12171 ($dff) port Q[0] of cell $procdff$12177 ($adff) Warning: multiple conflicting drivers for c port Q[0] of cell $procdff$12170 ($dff) port Q[0] of cell $procdff$12176 ($adff)

This is probably synthesized to two sets of DFFs that drive the same output. One is positive edge and one is negative.

so basically cant have this logic synthesized in sky130 ? @Matthew Guthaus

That won't synthesize in any technology really. It's bad Verilog

This cant be synthesized, you can do this by having a mux whose select pin is clock signal , and realize this logic as a workaround

If you're trying to make a dual-edged triggered flip-flop, this older thread from Stefan Schippers might be relevant https://open-source-silicon.slack.com/archives/C017P3RAD42/p1645654029880779 We were able to take that idea and synthesize it using openlane, but haven't quite done a gate level verification yet so not sure if it would work, but it looks promising https://github.com/3x10e8/fossi_cochlea/blob/main/verilog/final_verilog/gray_tree/edge_ff_gray.v