Hi, new designer here! I am trying to design an analog switch that can choose between two inputs, VREFH and VREFL with range -3.3V to +3.3V. The design consists of 3 blocks, • 1.8V switch logic to switch the level shifters between level and 0V. • 1 stage up level shifter to 3.3V and 2 stage down level shifter to -3.3V • 2 transmission gates driven by the level shifters. The first iteration made with help of @Stefan Schippers with only positive range 0-3.3V and using only the up level shifter works perfectly incl. ranges like VREFL= 0V to VREFH= 0.1V. Attached are my results of the negative voltage shifter and its switching output seems to be correct at -3.3V or 0V (the same for the level up shifter at +3.3V or 0). The output of the VREFH transmission gate driven by the level up shifter works great. The issue is with the output of the VREFL transmission gate. It can output a correct level until VREFL = -3V but quickly breaks down to what seems -3.3V/2 when VREFL = -3.3V. When combining the outputs of the transmission gates the output is not driven to its desired strength offsetting the output of the upper transmission gate with the output of the bottom transmission gate. I have played a lot with tweaking the L/W values of the level down shifter as well as the transmission gates but lack a deeper understanding what is wrong. Is there a magic value that makes this design work or is the design itself at fault? Any insight is much appreciated!

Your up level shifter looks ok, but the down level shifter may have some problems. With up level shifters, the high input is not enough to turn off a lower voltage input pmos with a high source. So the output of the nmos is fed back in to the opposite pmos. Only one of the nmos is on at one time. Your down level shifter is trying to convert a VDD/VSS signal into a VSS/VSSA signal. Either the high voltage or the low voltage should match the input. Currently you have A and Abar into nmos with VSSA source. Since the lowest A or Abar will be is VSS, both of these nmos will be on simutaneously. I suggest you convert the VDD/VSS signal to a VDD/VSSA signal, by first attaching the source of M21 and M22 to VDD and then inputing A and Abar into the pmos M21 and M22 and then cross the outputs to the nmos M15 and M16. Only one of the pmos will be on at a time and the feedback will shut off the corresponding nmos. This is the signal you want for your VREFL transfer gate. Using a VSS/VSSA signal on the VREFL signal will not allow it to pass without a drop when VREFL < Vth. You can then take this VDD/VSSA output and run it through a VSS/VSSA buffer to reduce the high voltage.

Thank you for your analysis! I will change my level down converter and let you know the result.

If I understand your circuit correctly, when

IN

is high,

OUTU=VREFH

and when

IN

is low,

OUTD=VREFL

. This appears to be working. I think the problem you're seeing is what happens to

OUTD

when

IN

is high and the M6/M12 transfer gate is off.

OUTU

is connected to a capacitor which may provide a pull down when M11/M5 is off, but there is no corresponding pull up when M6/12 is off. Is the red

OUT

supposed to be

OUTD

? You might want to provide an additional set of transfer gates to force

OUTU

and

OUTD

to VSS when not shorted to

VREFH

or

VREFL

respectively.

@Mitch Bailey Thanks again Mitch, you helped me change my thinking about analyzing the problem in terms of it being on or off. In the case of transmission gates those terms have special meaning, ON being passing input signal 1:1 to output and OFF being in high impedance state (and thus no driving output to ground when off). I proceeded to isolate the transmission gates from the rest of the circuit and removed the capacitor to make it as simple as possible. In the OFF test of a single transmission gate I set the control signal to NMOS=VSSA and PMOS its complement (VDDA). Regardless of input source (if input source is within range of VSSA and VDDA of course), the output remained in high impedance. In the ON test is set the NMOS=VDDA and PMOS its complement (VSSA). Now the input source is 1:1 copied to output (again if input source is within range of VSSA and VDDA). Great problem solved. A lessons learned was that my design process was a bit backwards. Starting with the level shifters instead of testing the transmission gate with the new negative voltage requirement. The simulation of the old design pictured above worked in the range of -2.1V to +2.1V throwing me a bit off and mostly likely would result in issues when fabricated. In the end a two stage level down shifter was not needed, and could simple be integrated by extending the level up shifter, removing a potential timing issue in the process. In addition no driving to ground was needed as it always switches between VREFL and VREFH. Again thanks for your guidance. Finally, 1) can you point me to some resources how to decide the W and L of the transistors? Based on this bin resource that has a list of physical measurements I have an idea of an acceptable range (https://github.com/google/skywater-pdk-libs-sky130_fd_pr/blob/f62031a1be9aefe902d6[…]7436/cells/pfet_g5v0d10v5/sky130_fd_pr__pfet_g5v0d10v5.bins.csv) For the 1.8V input logic I am using L=150nm, the minimum and a width ratio of PMOS:NMOS of 2:1. Question 2) Can the same ratio be use for the thicker oxide 5V transistors (which I use at 3.3V) or is going from 1.8V to 5V non-linear? 3) The smallest width would result in the smallest gate capacitance and thus switching speed?

@Steven Bos do also a transient analysys to verify the switching speed. In some cases an insufficient (or excessive) sizing can lead to extremely slow transitions, and during transitions there will also be a huge curent consumption from the supplies. In general mos devices with cross-connected gates must be weak (small W, long L) and the other drive transistors must be strong (large W, short L). Also if you use +3.3V and -3.3V the gate to source or gate to drain voltage may be higher than 5V. In this case you might want to evaluate cascode protections.

Wonderful @Stefan Schippers and @Mitch Bailey. I will explore cascode protection or reduce requirement to -2.5 +2.5V.