Hi, just some general questions: 1. In SDC, does parameters such as

set_max_fanout

and

set_driving_cell

sets the max fanout and cell model for the output ports of the top level of the design or is it for every cell in the design? 2. In openlane variable configurations, does the parameters such as

SYNTH_MAX_FANOUT

and

SYNTH_DRIVING_CELL

sets the max fanout and cell model for the output ports of the top level of the design or is it for every cell in the design? Both of them (SDC and openlane variables) is said to configure the output ports , but Im not sure if those ports are just the ports of the top level design or all output ports for every cell in the design. 3. Third question is, the tcl script

/openlane/scripts/openroad/sta.tcl

is used in pre-layout STA in openlane and I noticed that the liberty file read is only

LIB_TYPICAL

(or the

LIB_SYNTH_COMPLETE

). However in a workshop I attended before, the instructor manually read the liberty file inside openroad and the liberty file read is both the

LIB_SLOWEST

and

LIB_FASTEST

and he used

read_libery -max

and

read_liberty -min

commands (unlike in

sta.tcl

where there is no -min or -max specified on the command) . Why did the instructor need to read the slowest and fastest library if only the typical library is enough (just like what is done in openlane pre-layout STA)? Thanks

3. The sta.tcl report is designed to be read by rtl developers to understand how much the timing change. Having hold time does not give them anything useful as there is no clock tree.

Thanks @Arman Avetisyan