Anyone know the reason of the error?
# openlanea
Awadhesh
09/12/2022, 6:15 PMAnyone know the reason of the error?
a
Arman Avetisyan
09/12/2022, 6:41 PMToo many possible reasons.
Too low area, too high density, too low density, too huge area, etc.
Need following data at least: Verilog, Config.json/tcl.
Preferably an issue, filled according to form, on GitHub of OpenLane.
a
Awadhesh
09/12/2022, 6:43 PMthanks i got this it's congestion related problem
thanks for your reply
Awadhesh
09/12/2022, 6:45 PMBut in the generated def files there are too much DRC violations.Can you tell me the possible reasons? @Arman Avetisyan
v
Vijayan Krishnan
09/13/2022, 5:59 AMfile a github issue with test case. Load .def into OpenORAD GUI along with
drc.rpta
Awadhesh
09/13/2022, 3:47 PMthanks i see that