Hello, can someone help me how to solve this probl...
# sky130
b
Hello, can someone help me how to solve this problem, it seems that yosys generates REG which is not supported by opensta
a
Steps to reproduce? My guess you are trying to load a verilog RTL into OpenSTA which expectes a verilog netlis
b
nope, i just run the openlane's flow, i notice that the netlist has "reg"
So, do you know how to handle this problem?
yosys-generated verilog has this syntax error....
f
I had a problem like this before, turns out yosys couldn't synthesize my rtl correctly. Run each module seperately through openlane to spot the problem and then comment out parts of the module to exactly spot the problem. And maybe check yosys's output for any hints or warnings.
v
@b224hisl can you share your git repo link which has source files