Hello, can someone help me how to solve this problem, it seems that yosys generates REG which is not supported by opensta
a
Arman Avetisyan
09/12/2022, 2:02 PM
Steps to reproduce? My guess you are trying to load a verilog RTL into OpenSTA which expectes a verilog netlis
b
b224hisl
09/12/2022, 2:12 PM
nope, i just run the openlane's flow, i notice that the netlist has "reg"
b224hisl
09/12/2022, 2:12 PM
So, do you know how to handle this problem?
b224hisl
09/12/2022, 2:13 PM
yosys-generated verilog has this syntax error....
f
Farhad Modaresi
09/12/2022, 2:35 PM
I had a problem like this before, turns out yosys couldn't synthesize my rtl correctly. Run each module seperately through openlane to spot the problem and then comment out parts of the module to exactly spot the problem.
And maybe check yosys's output for any hints or warnings.
v
Vijayan Krishnan
09/13/2022, 5:50 AM
@b224hisl can you share your git repo link which has source files