For satisfying the precheck consistency check, I a...
# analog-design
k
For satisfying the precheck consistency check, I am currently flattening my analog circuits and am able to pass all checks. However, I see that some of the layers I used in the layout get dropped after the flattening. Is there a way to resolve the consistency check issue without having to completely flatten my own layout ? Please note: I am designing my circuit in Cadence Virtuoso, and simply generate the .gds file of my design, integrate with user_analog_project_wrapper.gds and upload this file along with the default netgen, xschem files (unedited) to the efabless platform as a tar file.
m
I would kindly suggest that you not flatten your design. That is hack to bypass some of the consistency checks in pre-check. The precheck should have been fixed last week. Can you post the error that you get with the hierarchical gds? Also the spice netlist from the schematic should go in
netgen/user_analog_project_wrapper.spice
k
actually spice netlisting is the issue. I am just downloading the user_analog_project_wrapper gds (https://github.com/efabless/caravel/blob/main/gds/user_analog_project_wrapper.gds.gz), importing this GDS into Cadence, and placing my chip layout view into this. Then, I export the GDS of this combined layout, rename it as user_analog_project_wrapper.gds and and copy this to the caravel_user_project_analog_folder. All other files including spice netlisting files remain the same as the default in https://github.com/efabless/caravel_user_project_analog . I understand that I should update the spice netlist, but am not using the open-source tool flow currently because of time constraints.
The chip that I place in the wrapper actually doesn't connect to any of the pins/pads in the wrapper, so I was wondering if I could add a simple line or two to the netlist and pass the consistency check. But I am not familiar with the syntax of netgen/xschem files.
this image shows the exact error message, 'full_chip' is the name of my chip layout view
m
The
netgen
here is just a directory. Put your cdl in that directory with a
.spice
extension. Do you do LVS in Cadence?
k
No I don't do top-level LVS in Cadence as I don't have the schematic view for the wrapper. I thought that the foundry would worry only about the verification of DRC rules, minimum layer density etc, and not be concerned with the LVS.
m
You are correct in that the foundry does not worry about LVS. Google/efabless on the other hand may require it in the future.