Hi all, I am looking for a taped out project that has multiple clock domains and domain crossing. @Matt Venn suggested to look at the sdc files of each project but that is difficult as the repos are not consistent (structure-wise). Did anyone here came across any such design?

I have used multiple clock domain across some of my block 1. https://github.com/dineshannayya/riscduino/blob/master/openlane/uart_i2cm_usb_spi_top/base.sdc 2. https://github.com/dineshannayya/riscduino/blob/master/openlane/ycr_intf/base.sdc 3. https://github.com/dineshannayya/riscduino/blob/master/openlane/wb_host/base.sdc Final Top-level SDC https://github.com/dineshannayya/riscduino/blob/master/sta/sdc/caravel.sdc

+ @Xanthos Vlachos Thank you Dinesh. First of all great work! And well documented. Is any of the tape outs silicon validated?

Still waiting for My first MPW-2 Silicon. I have regularly upgraded RISCDUINO Single Core/Dual Core/Quad Core database from MPW-3 onward.