I am struggling the pass pre-check for mpw7, my design has 2 2K OpenRAM macros I got DRC error of Metal3_gt_3um_spacing_to_unrelated_m3_lt_0dot4um_met3dot3d (Metal3 > 3um spacing to unrelated m3 < 0.4um (met3.3d)) There are 60 violations and all of them are at the edges of OpenRAM macros this is the macro.cfg: instr_ram 240 2950 N data_ram 1100 2950 N config.tcl set ::env(GRT_OBS) "\ li1 240 2950 923.1 3366.54,\ met1 240 2950 923.1 3366.54,\ met2 240 2950 923.1 3366.54,\ met3 240 2950 923.1 3366.54,\ met4 240 2950 923.1 3366.54,\ li1 1100 2950 1783.1 3366.54,\ met1 1100 2950 1783.1 3366.54,\ met2 1100 2950 1783.1 3366.54,\ met3 1100 2950 1783.1 3366.54,\ met4 1100 2950 1783.1 3366.54,\ met5 0 0 2920 3520" openram lef: MACRO sky130_sram_2kbyte_1rw1r_32x512_8 CLASS BLOCK ; SIZE 683.1 BY 416.54 ; more detail is here: https://open-source-silicon.slack.com/archives/C016UL7AQ73/p1633433046163200

Looks like it's related to this https://open-source-silicon.slack.com/archives/C01E06TUSC9/p1625161999110600 Are you getting failures or just warnings on the precheck? Some drc checks are just "suggestions".

it is a fail :l