Hi everyone, in the tapeout process .. i have edited the user_proj_example file according to my design (frequency divider) .. i also ran the pre-check and the precheck had passed .. I tried editing the testbench according to my design and running the simulation process but failed to do so .. can someone please help me to edit the testbench according to my design .. The git below is the git where i am tracking progress from initial start of work. (It has my original verilog code and the working normal verilog testbench) https://github.com/DantuNandiniDevi/iiitb_freqdiv The git below is the caravel git in which i uploaded the edited user_proj_example and the modifed testbench which is not working. https://github.com/DantuNandiniDevi/iiitb_freqdiv_caravel