hi , I am using hierarchical flow with BLOCKA and ...
# openlaner
Ryan R
09/09/2022, 5:54 AMhi , I am using hierarchical flow with BLOCKA and BLOCKB , done seperately in openlane and plugged in the lib , lef and GDS to TOP . But getting PDN issue. What are changes needed to be done in config.tcl for TOP. So that the power hookup happens properly..
[INFO]: Generating PDN...
[ERROR]: during executing openroad script /openlane/scripts/openroad/pdn.tcl
[ERROR]: Exit code: 1
[ERROR]: full log: designs/RRAM_CONTROLLER/runs/0909/logs/floorplan/7-pdn.log
[ERROR]: Last 10 lines:
[WARNING PSM-0038] Unconnected PDN node on net VPWR at location (2446.200um, 2298.400um), layer: 2.
[WARNING PSM-0038] Unconnected PDN node on net VPWR at location (2451.600um, 2298.400um), layer: 2.
[WARNING PSM-0038] Unconnected PDN node on net VPWR at location (2457.000um, 2298.400um), layer: 2.
[WARNING PSM-0038] Unconnected PDN node on net VPWR at location (2462.400um, 2298.400um), layer: 2.
[WARNING PSM-0038] Unconnected PDN node on net VPWR at location (2467.800um, 2298.400um), layer: 2.
[WARNING PSM-0038] Unconnected PDN node on net VPWR at location (2473.200um, 2298.400um), layer: 2.
[WARNING PSM-0038] message limit reached, this message will no longer print
v
Vijayan Krishnan
09/09/2022, 6:07 AMshare
config.tclr
Ryan R
09/09/2022, 6:10 AM# Design
set ::env(DESIGN_NAME) "RRAM_CONTROLLER"
set ::env(PDK) {sky130B}
set ::env(VERILOG_FILES) [glob ./designs/RRAM_CONTROLLER/src/top_0709.v]
set ::env(CLOCK_PERIOD) "10.000"
set ::env(CLOCK_PORT) "clk"
set ::env(CELL_PAD) 4
set ::env(EXTRA_LIBS) "./designs/RRAM_CONTROLLER/RRAM_ANALOG.lib ./designs/RRAM_CONTROLLER/sync_fifo_16x16.lib ./designs/RRAM_CONTROLLER/sync_fifo_32x64.lib"
set ::env(EXTRA_LEFS) { ./designs/RRAM_CONTROLLER/RRAM_ANALOG.lef ./designs/RRAM_CONTROLLER/sync_fifo_16x16.lef ./designs/RRAM_CONTROLLER/sync_fifo_32x64.lef}
set ::env(DIE_AREA) {0.0 0.0 2500 2500 }
set ::env(PL_TARGET_DENSITY) {0.20}
set ::env(FP_SIZING) "absolute"
#set ::env(TAP_DECAP_INSERTION) {0}
#set ::env(FILL_INSERTION) {0}
#set ::env(QUIT_ON_TR_DRC) {0}
#set ::env(FP_PDN_ENABLE_MACROS_GRID) {0}
#set ::env(ROUTING_OPT_ITERS) {10}
set ::env(EXTRA_GDS_FILES) {./designs/RRAM_CONTROLLER/RRAM_ANALOG.GDS ./designs/RRAM_CONTROLLER/sync_fifo_16x16.magic.gds ./designs/RRAM_CONTROLLER/sync_fifo_32x64.magic.gds}
#set ::env(FP_PIN_ORDER_CFG) $::env(OPENLANE_ROOT)/designs/rram_wrapper_16x16/pin_order.cfg
set ::env(MACRO_PLACEMENT_CFG) [glob $::env(DESIGN_DIR)/macro.cfg]
set ::env(SYNTH_BUFFERING) {0}
set ::env(SYNTH_NO_FLAT) {1}
set ::env(PL_BASIC_PLACEMENT) {1}
#set ::env(TAP_DECAP_INSERTION) {0}
#set ::env(FP_PDN_CHECK_NODES) 0
set ::env(FP_PDN_ENABLE_MACROS_GRID) {1}
set filename ./designs/$::env(DESIGN_NAME)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
source $filename
}
m
Mitch Bailey
09/09/2022, 6:13 AMAre you using
FP_PDN_MACRO_HOOKS👀 1
r
Ryan R
09/09/2022, 6:14 AM@Mitch Bailey this is not at the user_project_wrapper level though , will go to userproject. This is still at module level.
m
Mitch Bailey
09/09/2022, 6:19 AMSorry, that was just a reference to another design. Anytime you want to connect your macros to power, use
FP_PDN_MACRO_HOOKSconfig.tclr
Ryan R
09/09/2022, 6:20 AMset ::env(FP_PDN_ENABLE_MACROS_GRID) {1}
set ::env(FP_PDN_MACRO_HOOKS) "sync_fifo_16x16 VPWR VPWR , sync_fifo_32x64 VPWR VPWR"
set ::env(VDD_PIN) {VPWR vdd}
set ::env(GND_PIN) {VGND gnd}
Ryan R
09/09/2022, 6:22 AM@Mitch Bailey @Vijayan Krishnan - my macros sync_fifo* have VPWR and VGND since done in openlane....Have set above vars ,,, but still doesnt work
v
Vijayan Krishnan
09/09/2022, 6:26 AMcan you share repo link with rtl file location? Is
USE_POWER_PINSr
Ryan R
09/09/2022, 6:26 AMThis is module level , hence not defining
USE_POWER_PINS . let me share quickly...v
Vijayan Krishnan
09/09/2022, 6:27 AMare you trying to use caravel flow for mpw shuttle or exploring with OpenLane flow?
👀 1
m
Mitch Bailey
09/09/2022, 6:27 AMThey changed the format. Try
set ::env(FP_PDN_MACRO_HOOKS) "sync_fifo_16x16 VPWR VGND VPWR VGND, sync_fifo_32x64 VPWR VGND VPWR VGND"r
Ryan R
09/09/2022, 6:27 AMthis is the module level at openlane.. I will move to caravel once this design is through openlane....
v
Vijayan Krishnan
09/09/2022, 6:29 AMuse
set ::env(DESIGN_IS_CORE) 0r
Ryan R
09/09/2022, 6:30 AMhere is my latest set , still fails :
set ::env(DESIGN_NAME) "RRAM_CONTROLLER"
set ::env(PDK) {sky130B}
set ::env(VERILOG_FILES) [glob ./designs/RRAM_CONTROLLER/src/top_0709.v]
set ::env(CLOCK_PERIOD) "10.000"
set ::env(CLOCK_PORT) "clk"
set ::env(CELL_PAD) 4
set ::env(EXTRA_LIBS) "./designs/RRAM_CONTROLLER/RRAM_ANALOG.lib ./designs/RRAM_CONTROLLER/sync_fifo_16x16.lib ./designs/RRAM_CONTROLLER/sync_fifo_32x64.lib"
set ::env(EXTRA_LEFS) { ./designs/RRAM_CONTROLLER/RRAM_ANALOG.lef ./designs/RRAM_CONTROLLER/sync_fifo_16x16.lef ./designs/RRAM_CONTROLLER/sync_fifo_32x64.lef}
set ::env(DIE_AREA) {0.0 0.0 2500 2500 }
set ::env(PL_TARGET_DENSITY) {0.20}
set ::env(FP_SIZING) "absolute"
#set ::env(TAP_DECAP_INSERTION) {0}
#set ::env(FILL_INSERTION) {0}
#set ::env(QUIT_ON_TR_DRC) {0}
#set ::env(FP_PDN_ENABLE_MACROS_GRID) {0}
#set ::env(ROUTING_OPT_ITERS) {10}
set ::env(EXTRA_GDS_FILES) {./designs/RRAM_CONTROLLER/RRAM_ANALOG.GDS ./designs/RRAM_CONTROLLER/sync_fifo_16x16.magic.gds ./designs/RRAM_CONTROLLER/sync_fifo_32x64.magic.gds}
#set ::env(FP_PIN_ORDER_CFG) $::env(OPENLANE_ROOT)/designs/rram_wrapper_16x16/pin_order.cfg
set ::env(MACRO_PLACEMENT_CFG) [glob $::env(DESIGN_DIR)/macro.cfg]
set ::env(SYNTH_BUFFERING) {0}
set ::env(SYNTH_NO_FLAT) {1}
set ::env(PL_BASIC_PLACEMENT) {1}
#set ::env(TAP_DECAP_INSERTION) {0}
#set ::env(FP_PDN_CHECK_NODES) 0
set ::env(FP_PDN_ENABLE_MACROS_GRID) {1}
set ::env(FP_PDN_MACRO_HOOKS) "sync_fifo_16x16 VPWR VGND VPWR VGND,sync_fifo_32x64 VPWR VGND VPWR VGND"
set ::env(VDD_PIN) {VPWR vdd}
set ::env(GND_PIN) {VGND gnd}
set filename ./designs/$::env(DESIGN_NAME)/$::env(PDK)_$::env(STD_CELL_LIBRARY)_config.tcl
if { [file exists $filename] == 1} {
source $filename
}
set ::env(DESIGN_IS_CORE) 0
v
Vijayan Krishnan
09/09/2022, 6:33 AMNo
VERILOG_FILES_BLACKBOXr
Ryan R
09/09/2022, 6:34 AM@Vijayan Krishnan - i have used in the the EXTRA_LIBS the macro libs... will this not do ??
my github repo : https://github.com/ratul619/OPENLANE
v
Vijayan Krishnan
09/09/2022, 6:35 AMset ::env(FP_PDN_CHECK_NODES) 0r
Ryan R
09/09/2022, 6:36 AM@Vijayan Krishnan - doesnt work , flow fails
[STEP 7]
[INFO]: Generating PDN...
[ERROR]: during executing openroad script /openlane/scripts/openroad/pdn.tcl
[ERROR]: Exit code: 1
[ERROR]: full log: designs/RRAM_CONTROLLER/runs/0909_1/logs/floorplan/7-pdn.log
[ERROR]: Last 10 lines:
33# 0x00007F5C9E610F1E in /lib64/libtcl8.5.so
34# Tcl_EvalEx in /lib64/libtcl8.5.so
35# Tcl_Eval in /lib64/libtcl8.5.so
36# sta::sourceTclFile(char const*, bool, bool, Tcl_Interp*) in openroad
37# ord::tclAppInit(Tcl_Interp*) in openroad
38# Tcl_Main in /lib64/libtcl8.5.so
39# main in openroad
40# __libc_start_main in /lib64/libc.so.6
41# 0x0000000001028727 in openroad
child process exited abnormally
v
Vijayan Krishnan
09/09/2022, 6:37 AMwhich version of openlane used?
r
Ryan R
09/09/2022, 6:38 AMopenlane 01e951092150ee8619286b0807ee263198b5ea6d
v
Vijayan Krishnan
09/09/2022, 6:39 AMIts june 2nd commit. Update your openlane commit to latest and try again. few configuration name got updated. plz accordingly change your
config.tclr
Ryan R
09/09/2022, 6:43 AMFor updating openlane only , what command to use
v
Vijayan Krishnan
09/09/2022, 6:45 AMr
Ryan R
09/09/2022, 6:46 AMhow to discard changes ??
Updating 01e9510..63b5966
error: Your local changes to the following files would be overwritten by merge:
designs/README.md
scripts/base.sdc
scripts/tcl_commands/placement.tcl
scripts/yosys/synth.tcl
Please commit your changes or stash them before you merge.
Aborting
v
Vijayan Krishnan
09/09/2022, 6:53 AMits seems you changed those files. you can remove those files manually and pull again
r
Ryan R
09/09/2022, 6:57 AM@Vijayan Krishnan - using version below BUt getting same issue :
openlane 4476a58407d670d251aa0be6a55e5391bb181c4e
Ryan R
09/09/2022, 7:01 AM@Vijayan Krishnan - please check the github - have uploaded
a
Arman Avetisyan
09/09/2022, 7:03 AM1. create an issue on github to help keep track of things
2. Looks like you are using custom macros. They may use different layers other than met4. AFAIK If you use macro level flow it should not connect the met4 to met3 (assuming your pdn is on met3)
3. Need more information regarding structure of the macro cells used.
4. you need to connect the verilog power pins, unless you have only VPWR/VGND and using nets with the same name. Looks like you have vdd and vss nets that are unconnected
v
Vijayan Krishnan
09/09/2022, 7:19 AM@Ryan R
For hardening macro in hierarchical certain rule should followed. your fifo lef shows powered with met4. It may create issue at user_project_wrapper level.
I don't know what's your plan on this.
1. Use till met3 for routing max for fifo hardeing
2. top_0709 use met4 as max routing layer
3. user_project_wrapper use met5 as max routing layer
4. accordingly take care of power supply layers for each stage
r
Ryan R
09/09/2022, 7:19 AMok will try that
v
Vijayan Krishnan
09/09/2022, 7:22 AMFor step 1 &2 add
set ::env(DESIGN_IS_CORE) 0👍 1
r
Ryan R
09/09/2022, 7:25 AMvariable to control is : set ::env(RT_MAX_LAYER) {met5} correct
v
Vijayan Krishnan
09/09/2022, 7:26 AMyes
r
Ryan R
09/09/2022, 7:36 AMThanks. the PDN step crosssed w/o the above changes , but getting DRCS in detailed route... let me make the max metal layers changes in fifo and rerun...
a
Arman Avetisyan
09/09/2022, 7:46 AMIs fifo hardened using openlane?
If yes, keep in mind that timings are not going to be checked and you are going to have issues.
1. Do not use hardening unless its absolutely necessary
2. Do not use multiple level of hardening to save yourself some time.
3. Use openroad gui and load defs to be able to properly debug what is happening with PDN
r
Ryan R
09/09/2022, 7:48 AMactually , when i flattened the full design , i was having congestion issues. The ticket which i raised yesterday. But right now need to repllicate the issue again. Yes i agree on the timing front. im going to manage with SDC constraints
v
Vijayan Krishnan
09/09/2022, 9:29 AMset ::env(PL_BASIC_PLACEMENT) {1}set ::env(PL_BASIC_PLACEMENT) {0}r
Ryan R
09/09/2022, 9:29 AMlet me checkk!!
v
Vijayan Krishnan
09/09/2022, 9:37 AMhttps://github.com/The-OpenROAD-Project/OpenLane/issues/1341 this is the issue have you raised?
r
Ryan R
09/09/2022, 9:39 AMyes. i am re-running. with the var as 0 -- pls hold
Ryan R
09/09/2022, 9:41 AMset ::env(PL_BASIC_PLACEMENT) {0}
still fails :
[INFO]: Running Global Routing Resizer Timing Optimizations (log: designs/RRAM_CONTROLLER_flat/runs/0909_BP0/logs/routing/18-resizer.log)...
[ERROR]: during executing openroad script /openlane/scripts/openroad/resizer_routing_timing.tcl
[ERROR]: Log: designs/RRAM_CONTROLLER_flat/runs/0909_BP0/logs/routing/18-resizer.log
[ERROR]: Last 10 lines:
[INFO GRT-0101] Running extra iterations to remove overflow.
[INFO GRT-0197] Via related to pin nodes: 4217
[INFO GRT-0198] Via related Steiner nodes: 0
[INFO GRT-0199] Via filling finished.
[INFO GRT-0111] Final number of vias: 6212
[INFO GRT-0112] Final usage 3D: 50975
[ERROR GRT-0118] Routing congestion too high. Check the congestion heatmap in the GUI.
Error: resizer_routing_timing.tcl, 53 GRT-0118
child process exited abnormally
v
Vijayan Krishnan
09/09/2022, 9:42 AMin the github issue thread update
issue_template51 Views