Hi, I designed some analog circuits with a commercial EDA tool, integrated the GDS with the user_analog_project_wrapper (https://github.com/efabless/caravel/blob/main/gds/user_analog_project_wrapper.gds.gz), and submitted the design for precheck. It passes all of the checks except for 'Klayout BEOL'. This check shows 272 DRC violations, and points to a log file which details these errors. I tried to understand the log file, but I am finding it hard to clearly understand what these DRC violations are. Does anyone have suggestions as to how I can more clearly see these violations on my layout, or if someone has a general idea of which kind of errors/issues cause BEOL DRC violations ?

You can load the drc result file in klayout to see the results.

thanks, can you indicate which precise file should I load in Klayout, as there are quite a few of them in the database ?

I think it ends in

xml

. Does that help?

thanks it helps. I did view these files, was doubtful as they open in a web browser by default

klayout -> Tools -> Marker Browser

thank you, this works well

@KSHITIZ TYAGI How have you integrated skywater pdk with commercial EDA tool?

My university obtained access to the SKY PDK files required for installation and operation with Cadence Virtuoso. I think you do need to reach an agreement with efabless for this.