Hello, I'm trying to run LVS for a two stage op-amp. The

opamp_realcomp3_usefinger.spice

is generated from schematic and

opamp_realcomp3_usefinger_layout.spice

is extracted from magic. I used

lvs.tcl

to extract the layout and use

netgen.sh

to run netgen comparison. My circuit and netlist are matched but my subcircuit pins are not. If anybody has any hint to match the subckt pins that'd be really appreciated.

...
Class opamp_realcomp3_usefinger (0):  Merged 119 parallel devices.
Subcircuit summary:
Circuit 1: opamp_realcomp3_usefinger       |Circuit 2: opamp_realcomp3_usefinger       
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_01v8_lvt (88->3)        |sky130_fd_pr__pfet_01v8_lvt (12->3)        
sky130_fd_pr__nfet_01v8_lvt (38->4)        |sky130_fd_pr__nfet_01v8_lvt (14->4)        
sky130_fd_pr__cap_mim_m3_1 (1)             |sky130_fd_pr__cap_mim_m3_1 (1)             
sky130_fd_pr__res_high_po_2p85 (1)         |sky130_fd_pr__res_high_po_2p85 (1)         
Number of devices: 9                       |Number of devices: 9                       
Number of nets: 10                         |Number of nets: 10                         
---------------------------------------------------------------------------------------
Circuits match uniquely.
Netlists match uniquely.

Subcircuit pins:
Circuit 1: opamp_realcomp3_usefinger       |Circuit 2: opamp_realcomp3_usefinger       
-------------------------------------------|-------------------------------------------
(no pins)                                  |bias_0p7 **Mismatch**                      
(no matching pin)                          |vdd                                        
(no matching pin)                          |vss                                        
(no matching pin)                          |in_n                                       
(no matching pin)                          |in_p                                       
(no matching pin)                          |out                                        
---------------------------------------------------------------------------------------
Cell pin lists for opamp_realcomp3_usefinger and opamp_realcomp3_usefinger altered to match.
Cells failed matching, or top level cell failed pin matching.

Do you have pins draw in the layout? Pins are extracted as top level layout ports, but your file doesn't have any.

Thank you. Do you know how to create the pins? I used "label xxx n" on the respective metals. But it didn't work

Maybe http://opencircuitdesign.com/magic/commandref/port.html

Thank you I figured it out. Need to label and enable the "port" function...