https://open-source-silicon.dev logo
Join Slack
Powered by
Your macros don't appear to be connected to power....
# ieee-sscs-dc-22
m
Your macros don't appear to be connected to power. Are you using 
FP_PDN_MACRO_HOOKS
? See https://open-source-silicon.slack.com/archives/C02QMUGPUT1/p1662480901873339?thread_ts=1662312826.813479&cid=C02QMUGPUT1
m
Hi Mitch, thank you for your answer Macros are connected to the power on user_project_wrapper/config.tcl Following your instructions, I connected the macros to power on their respective config.tcl files but I'm getting the same LVS error. I pushed the last change to github: https://github.com/HALxmont/MixPix/
m
openlane/user_project_wrapper/config.tcl
has
Copy code
set ::env(FP_PDN_MACRO_HOOKS) "\
	pixel_macro0 vccd1 vssd1 vccd1 vssd1, \
	rlbp_macro0 vccd1 vssd1 vccd1 vssd1"
but 
verilog/gl/user_project_wrapper.v
only has 
pixel_macro0
Looks like 
rlbp_macro
is missing. Which is strange because it shows up in the previous LVS resutls.
😲 2
m
mmm you're right, the netlist doesn't have the rlbp_macro. I will investigate this on the logs files after synthesis
Hi, just for issue tracking. The problem was solved by changing the size of the macros, I recommend using a size for each macro at least 250x250um Also, regarding to the missing 
pixel_macro0
in 
verilog/gl/user_project_wrapper.v
It's expected that the macro didn't appear in 
verilog/gl/user_project_wrapper.v
because the flow ended with errors, and the file that we were seeing was generated by the last experiment that ended without errors
👍 1
5 Views
Open in Slack
PreviousNext
Powered by