@Tim Edwards Question regarding WB-interface (or LA-interface) hold time checks. The insertion delay of the wb_clk_i clock domain depends on the register load. I measured 0.2 ns to > 6ns insertion delay depending on the register load. (Average insertion delay on a balanced wb_clk_i clock domain). IMHO this generates hold time issues in one interface direction, depending on the register load, unless you are lucky. So the question is: Where in the flow do we check for hold time violations of the WB\LA interfaces ? Even if the STA would support hierarchial SDFs\netlists, I'm still wondering if the STA constraints force the STA to come up with correct hold time reports through the WB\LA interfaces. Forgive me, I’m probably totally wrong with this thinking, but I try to understand it since I heard about the flow and I’m still wondering. Thanks a lot for your answer, cheers, Tobias

We have had a number of discussions about this; the only half-decent solution for timing between the management SoC and the user project area is to add a lot of margin to the constraints; but since the user area is synthesized separately, I don't know how well that actually works in practice. Probably @mshalan would have the best answer to that.

Yes, this is missing as far as I know. We just faced a similar issue with the tinytapeout scan chain. We weren't able to get a top level timing analysis, so we built enough margin into the design itself.

ADDING minimal delays, w/o knowing the given insertion delay of the mgmt. core is not practical, because this would mean a few ns delay with roughly 15 buffers per ns. Synthesis tools have never been good in adding minimal delays. Remember, we are talking about a 0.2ns to > 6 ns insertion delay variation.

Thanks for doing this Tobias

I had been thinking of something along these lines, but I had not worked out what the signaling actually looks like or written anything down. I'm all in favor of this proposal.

In order to come to a conclusion with this discussion, I uploaded an app note on github: https://github.com/cloudxcc/CaravelAppNotes/tree/main/AN_WBHT

Thanks, that's very helpful.

I think the adjustment should be done on the user side. A change in the mgmt core is not needed. Theoretically it can be done in the mgmt core, but it does not really have any advantage and the mgmt WB signals would not be compliant to the spec anymore, which creates unnec. room for discussions.