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hi, I am having LVS issues, I assume for power pin...
# openlane
b
hi, I am having LVS issues, I assume for power pins there are 6 hardened macros, 2 of them are 2K openram, top modul (user_project_wrapper) has only macro instantiations in LVS log, it says 5 pins mismatch LVS reports: net count difference = 5 device count difference = 0 unmatched nets = 5 unmatched devices = 5 unmatched pins = 0 property failures = 0 Total errors = 15 I found that vccd1 = 5 | vccd1 = 8 vssd1 = 6 | vssd1 = 8 in 30-user_project_wrapper.lef.log i attached config, wrapper and LVS logs any help is appreciated Regards,
user_project_wrapper.vconfig.tcl30-user_project_wrapper.lvs.lef.log30-lef.log28-write_powered_def.log30-user_project_wrapper.lef.log
m
Looks like your tie cell 
sky130_fd_sc_hd__conb_1
is not connected to power or ground at the top level.
b
Actually I also don't get why there is a cell in top module, since the wrapper only contains macros and connections
m
Looks like you've attached the verilog rtl. Can you attach the gl verilog?
b
user_project_wrapper_gl.v
user_project_wrapper_gl.v
user_project_wrapper_gl.v
user_project_wrapper_gl.v
I am trying to attach the file 😄
as downloadable but slack somehow expands it 😄
m
I can download.
Need the powered gate level netlist.
b
is it in the final folder ?
user_project_wrapper_final.v
user_project_wrapper_final.v
i think that 5 pins could be sky130_fd_sc_hd__conb_1 TIE_ZERO_zero_ (.VGND(vssd1), .VNB(vssd1), .VPB(vccd1), .VPWR(vccd1), .LO(zero_));
This TIE_ZERO module could be inserted by OR due to my addition to floorplan.tcl set tielo_cell [lindex $::env(SYNTH_TIELO_PORT) 0] set tielo_port [lindex $::env(SYNTH_TIELO_PORT) 1] set tiehi_cell [lindex $::env(SYNTH_TIEHI_PORT) 0] set tiehi_port [lindex $::env(SYNTH_TIEHI_PORT) 1] insert_tiecells "$tielo_cell/$tielo_port" -prefix "TIE_ZERO_" insert_tiecells "$tiehi_cell/$tiehi_port" -prefix "TIE_ONE_"
well I found a mistake .spi_master_sdi1(wb_dat_i[0]) actually there is no wb_dat_i signal, it is wbs_dat_i why up to LVS no tool caught that I dont understand this causes to 1'bx in gl of synthesis
👍 1
m
do you not have `default_nettype none in your verilog?
would be good to add that to catch these
also grep Warning in the yosys synth log
v
@Burak Aykenar Have you fixed the LVS issue?
b
LVS reports: net count difference = 1 device count difference = 0 unmatched nets = 1 unmatched devices = 0 unmatched pins = 0 property failures = 0 Total errors = 2 at least only 1 net now 😄
Subcircuit summary: Circuit 1: user_project_wrapper |Circuit 2: user_project_wrapper -------------------------------------------|------------------------------------------- axi_node_intf_wrap (1) |axi_node_intf_wrap (1) mba_core_region (1) |mba_core_region (1) sky130_sram_2kbyte_1rw1r_32x512_8 (2) |sky130_sram_2kbyte_1rw1r_32x512_8 (2) clk_rst_gen (1) |clk_rst_gen (1) peripherals (1) |peripherals (1) Number of devices: 6 |Number of devices: 6 Number of nets: 3789 Mismatch |Number of nets: 3788 Mismatch --------------------------------------------------------------------------------------- NET mismatches: Class fragments follow (with fanout counts): Circuit 1: user_project_wrapper |Circuit 2: user_project_wrapper --------------------------------------------------------------------------------------- Net: vccd1 |Net: vccd1 axi_node_intf_wrap/vccd1 = 1 | axi_node_intf_wrap/vccd1 = 1 mba_core_region/vccd1 = 1 | mba_core_region/vccd1 = 1 sky130_sram_2kbyte_1rw1r_32x512_8/vccd1 | sky130_sram_2kbyte_1rw1r_32x512_8/vccd1 peripherals/vccd1 = 1 | peripherals/vccd1 = 1 | clk_rst_gen/vccd1 = 1 | Net: clk_rst_gen_i/vccd1 |(no matching net) clk_rst_gen/vccd1 = 1 | --------------------------------------------------------------------------------------- Netlists do not match. Netlists do not match.
i have fixed 1'bx issues but now still 1 error, trying to identify that
v
insert_tiecells needs to be powered. So enabling following configuration will resolve LVS issue:
Copy code
set ::env(FP_PDN_ENABLE_RAILS) 0
set ::env(DIODE_INSERTION_STRATEGY) 0
set ::env(FILL_INSERTION) 0
set ::env(TAP_DECAP_INSERTION)
b
actually since I got off constant assignments in the top module, I think that I can remove insert_tiecells from floorplan.tcl, which I did, and now it passed Detailed Routing stage, now it is running XOR, hope this time no LVS error occurs
👍 1
m
I always try to keep top level just for wires
b
I found the problem in synthesis.chk.rpt file: 13. Executing CHECK pass (checking for obvious problems). Checking module user_project_wrapper... Warning: multiple conflicting drivers for user_project_wrapper.\io_in [16]: port tdo_o[0] of cell core_region_i (mba_core_region) module input io_in[16] Warning: Wire user_project_wrapper.\user_irq [2] is used but has no driver. Warning: Wire user_project_wrapper.\user_irq [1] is used but has no driver. Warning: Wire user_project_wrapper.\user_irq [0] is used but has no driver. Found and reported 4 problems. so it seems that I connected io_in signal to an output of a module, that seems to create LVS error running again after debugging it ...
v
@Burak Aykenar multiple conflicting driver should be reported as error and flow should stop. I think you can raise enhancement proposal with this RTL code. So we can save our run-time, not to wait till LVS check
b
I still has LVS issues. I continue on #lvs channel, any help is appreciated https://open-source-silicon.slack.com/archives/C032Y8J3KHA/p1662557923878629
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