<@U017X0NM2E7> Is there a way to have lvs clean la...
# analog-design
s
@Mitch Bailey Is there a way to have lvs clean layout with taps only on higher levels of hierarchy but not on lower level cells? I had a layout where I was adding psubstrate taps only at a higher level but lvs fails, mentioning missing net for the tap in lower levels
m
By default, netgen will automatically flatten mismatched cells. This flattening can sometimes yield matches at a higher level even if the lower levels don't match. I flatten all the generated devices (pcells) before extracting and this sometimes gives results that are easier to understand.