Result are bit confusing and it's look like totally away from design assumption of 214Mhz to 168Mhz ? Design assumed : Constant + Half Trim Period * $itor(bcount) = 4x clock period Where Constant assumed : 1.168 and Half Trim Period: 0.012. As per silicon data, it's look like constant is : 2.545 and Half Trim Period: 0.149 ?