Hi all, I am trying to build the S130A PDK for doing analog design following the instructions in https://docs.google.com/document/d/1Lhw2pqrtm9ZJmXbdrflb0DODGaacu7CoabqjQpmeUZQ/edit#. When I run the command: 'make pdk-with-volare', I get the following error message: 'Makefile60 * multiple target patterns. Stop.' The makefile line #60 is: '$(DV_PATTERNS): verify-% : ./verilog/dv/% '. Could someone indicate if this needs to be modified, and what could be the issue ?

Sorry, not enough information for me to give you any advice. Could you upload the logs and show your environment variable settings.