I'm getting some strange issue when extracting the user_analog_wrapper to .spice netlist. First, I am using both vssd2 and vssa2. They are not connected in layout. Yet during ext2spice, all connections to vssa2 are replaced with vssd2, and the port vssa2 is removed in the subckt ports list. It also does a strange thing where it "shorts" vssd2 to vssd2 to itself. Second, I am not using gpio_noesd[10]. When I extract, this port is also missing from the ports list. Both of these issues are easily fixed up just by editing the spice file to pass the precheck tests, but I wanted to ask if these were indicative of some underlying issue

Did you pass the lvs?

@Xiaochen Ni: To get an analog wrapper circuit to pass LVS when you have shorted together any of the power supply domains, you need to place a metal resistor across the net close to one of the terminal pins. That allows the pin to keep its own net name and not get merged into the other supply net. You'll need to do that both in the layout and in the schematic. If you are extracting from magic, alternatively you can set the option

ext2spice short voltage

to keep shorted terminal names separated by adding zero-volt ideal voltage sources into the netlist. The zero-volt sources should be properly handled by netgen during LVS. I am not sure what the issue with

gpio_noesd[10]

is, though.

@Xiaochen Ni If you have vssa2 and vssd2 connected to the same substrate via ptaps, the nets will appear as shorted. You can prevent this by surrounding one of the regions with

isosub

81/53.

AH makes sense, thanks a lot