Hi, does anyone know if there is a transmission gate cell in HV standard cells? Thanks

There should not be. But there is a tristate buffer and mux. Why dou you need it?

passgates are usually never used in a standard cell library because these are bidirectional and do not isolate output from input. If you need one for an analog / mixed signal design (like for example for sampling an analog input) you can create your own symbol, if you are working with a schematic. (

sky130_tests/passgate.sym

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But sometimes transmission gates can be found in larger designs such as a data flip flop (eg. https://antmicro-skywater-pdk-docs.readthedocs.io/en/test-submodules-in-rtd/contents/libraries/sky130_fd_sc_hd/cells/dfxtp/README.html ) which is much more area efficient than using flip flop design with combinational logic found in most text books. Matt Venn made a nice video on that

@Steven Bos almost any standard cell library i have worked on has DFFs and latches implemented using transmission gates. However as you can easily see these are not 'visible' to the outside of the standard cell. Inputs are buffered as well as outputs. Cell is characterized and simulation and synthesis tools use the cell as a black box with the right timing info. What you will not see are transmission gates used as stand alone devices in a digital work flow (that is RTL - synthesis- placement- routing - layout) .

@Arman Avetisyan thanks. I need it for analog MUX

Then you can just implement it using transistors in analog flow.

@Abdulaziz in the

xschem_sky130/sky130_tests

test schematics there is a self-calibrating

tb_bandgap.sch

testbench that uses passgates:

Thanks!!